LAN89730 datasheet(134/218 Pages) MICROCHIP

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LAN89730

DS60001348A-page 134

 2013-2015 Microchip Technology Inc.

6.3.11

AUTOMATIC FLOW CONTROL CONFIGURATION REGISTER (AFC_CFG)

This register configures the mechanism that controls both the automatic- and software-initiated transmission of pause

frames and back pressure. Refer to Section 4.5.1, "Flow Control" for more information on flow control operation.

Address:

02Ch

Size:

32 bits

Note:

The device will not transmit pause frames or assert back pressure if the transmitter is disabled.

Bits

Description

Type

Default

31:24

RESERVED

23:16

Automatic Flow Control High Level (AFC_HI)

Specifies, in multiples of 64 bytes, the level at which flow control will trigger.

When this limit is reached, the chip will apply back pressure or will transmit a

pause frame, as programmed in bits [3:0] of this register.

During full-duplex operation, only a single pause frame is transmitted when

this level is reached. The pause time transmitted in this frame is programmed

in the Pause Time (FCPT) field of the Flow Control Register (FLOW), con-

tained in the MAC CSR space.

During half-duplex operation, each incoming frame that matches the criteria in

bits [3:0] of this register will be jammed for the period set in the BACK_DUR

field.

R/W

00h

15:8

Automatic Flow Control Low Level (AFC_LO)

Specifies, in multiples of 64 bytes, the level at which a pause frame is trans-

mitted with a pause time setting of zero. When the amount of data in the RX

Data FIFO falls below this level, the pause frame is transmitted. A pause time

value of zero instructs the other transmitting device to immediately resume

transmission. The zero time pause frame will only be transmitted if the RX

Data FIFO had reached the AFC_HI level and a pause frame was sent. A zero

pause time frame is sent whenever automatic flow control in enabled in bits

[3:0] of this register.

R/W

00h

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