HT48R50A datasheet(13/46 Pages) HOLTEK

13 / 46 page

HT48R50A-1

Rev. 1.10

July 2, 2001

Interrupt

The device provides an external interrupt and

internal timer/event counter interrupts. The

Interrupt Control Register (INTC;0BH) con-

tains the interrupt control bits to set the en-

able/disable and the interrupt request flags.

Once an interrupt subroutine is serviced, all

the other interrupts will be blocked (by clearing

the EMI bit). This scheme may prevent any fur-

ther interrupt nesting. Other interrupt re-

quests may occur during this interval but only

the interrupt request flag is recorded. If a cer-

tain interrupt requires servicing within the ser-

vice routine, the EMI bit and the corresponding

bit of the INTC may be set to allow interrupt

nesting. If the stack is full, the interrupt request

will not be acknowledged, even if the related in-

terrupt is enabled, until the SP is decremented.

If immediate service is desired, the stack must

be prevented from becoming full.

All these kinds of interrupts have a wake-up ca-

pability. As an interrupt is serviced, a control

transfer occurs by pushing the program counter

onto the stack, followed by a branch to a sub-

routine at specified location in the program

memory. Only the program counter is pushed

onto the stack. If the contents of the register or

status register (STATUS) are altered by the in-

terrupt service program which corrupts the de-

sired control sequence, the contents should be

saved in advance.

External interrupts are triggered by a high to

low transition of the INT and the related inter-

rupt request flag (EIF; bit 4 of INTC) will be set.

When the interrupt is enabled, the stack is not

full and the external interrupt is active, a sub-

routine call to location 04H will occur. The in-

terrupt request flag (EIF) and EMI bits will be

cleared to disable other interrupts.

The internal Timer/Event Counter 0 interrupt

is initialized by setting the Timer/Event Coun-

ter 0 interrupt request flag (T0F; bit 5 of INTC),

caused by a timer 0 overflow. When the inter-

rupt is enabled, the stack is not full and the T0F

bit is set, a subroutine call to location 08H will

occur. The related interrupt request flag (T0F)

will be reset and the EMI bit cleared to disable

further interrupts.

The internal timer/even counter 1 interrupt is

initialized by setting the Timer/Event Counter

1 interrupt request flag (;bit 6 of INTC), caused

by a timer 1 overflow. When the interrupt is en-

Bit No.

Label

Function

INTC

(0BH)

EMI

Controls the master (global) interrupt

(1= enabled; 0= disabled)

EEI

Controls the external interrupt

(1= enabled; 0= disabled)

ET0I

Controls the Timer/Event Counter 0 interrupt

(1= enabled; 0= disabled)

ET1I

Controls the Timer/Event Counter 1 interrupt

(1= enabled; 0= disabled)

EIF

External interrupt request flag

(1= active; 0= inactive)

T0F

Internal Timer/Event Counter 0 request flag

(1= active; 0= inactive)

T1F

Internal Timer/Event Counter 1 request flag

(1= active; 0= inactive)

Unused bit, read as "0"

INTC register

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