M30LW128D datasheet(5/57 Pages) STMICROELECTRONICS

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M30LW128D

SUMMARY DESCRIPTION

The M30LW128D is a 128 Mbit device that is com-

posed of two separate 64 Mbit M58LW064D Flash

memories. The device can be erased electrically

at block level and programmed in-system using a

2.7V to 3.6V (VDD) supply for the circuitry and a

1.8V to VDD (VDDQ) supply for the Input/Output

pins.

The bus width can be configured for x8 or x16 for

the devices available in the TSOP56 (14 x 20 mm)

and TBGA64 (10x13mm, 1mm pitch) packages.

The bus width is set to x16 for the devices avail-

able in the LFBGA88 (8x10mm, 0.8mm pitch)

package.

Each internal M58LW064D has 3 Chip Enable sig-

nals to allow up to 4 memories to be connected to-

gether without the use of additional glue logic. In

this way the address space is contiguous and the

microprocessor only requires one Chip Enable, E,

to control both memories.

The device is divided into 128 blocks of 1Mbit (2 x

64 x 1Mb) that can be erased independently so it

is possible to preserve valid data while old data is

erased. Program and Erase commands are written

to the Command Interface of the device. An on-

chip Program/Erase Controller (P/E.C) simplifies

the process of programming or erasing the device

by taking care of all of the special operations that

are required to update the memory contents. The

end of a Program or Erase operation can be de-

tected and any error conditions identified in the

Status Register. The command set required to

control the device is consistent with JEDEC stan-

dards.

The Write Buffer allows the microprocessor to pro-

gram from 1 to 16 Words in parallel, both speeding

up the programming and freeing up the micropro-

cessor to perform other work. A Word Program

command is available to program a single word.

Erase can be suspended in order to perform either

Read or Program in any other block and then re-

sumed. Program can be suspended to Read data

in any other block and then resumed. Each block

can be programmed and erased over 100,000 cy-

cles.

Individual block protection against Program or

Erase is provided for data security. All blocks are

protected during power-up. The protection of the

blocks is non-volatile; after power-up the protec-

tion status of each block is restored to the state

when power was last removed. Software com-

mands are provided to allow protection of some or

all of the blocks and to cancel all block protection

bits simultaneously. All Program or Erase opera-

tions are blocked when the Program Erase Enable

input VPEN is low.

The Reset/Power-Down pin is used to apply a

Hardware Reset to the enabled memory and to set

the device in power-down mode.

The STS signal is an open drain output that can be

used to identify the Program/Erase Controller sta-

tus. It can be configured in two modes: Ready/

Busy mode where a static signal indicates the sta-

tus of the P/E.C, and Status mode where a pulsing

signal indicates the end of a Program or Block

Erase operation. In both modes it can be used as

a system interrupt signal, useful for saving CPU

time. The STS signal is only available with the

TSOP56 and TBGA64 packages.

Each memory includes a 128 bit Protection Regis-

ter. The Protection Register is divided into two 64

bit segments, the first one is written by the manu-

facturer (contact STMicroelectronics to define the

code to be written here), while the second one is

programmable by the user. The user programma-

ble segment can be locked.

M30LW128D Datasheet(PDF) 5 Page - STMicroelectronics

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