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ADGS1412 Datasheet(PDF) 11 Page - Analog Devices

Part # ADGS1412
Description  Serially Controlled, 1.5 廓, On-Resistance, High Voltage, iCMOS, Quad SPST Switch
PDF  26 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADGS1412 Datasheet(HTML) 11 Page - Analog Devices

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ADGS1412
Data Sheet
Rev. 0 | Page 10 of 25
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
2
1
3
4
5
6
18
17
16
15
14
13
D4
S4
GND
VSS
S1
D1
D3
S3
VDD
NIC
S2
D2
ADGS1412
TOP VIEW
(Not to Scale)
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2. THE EXPOSED PAD IS CONNECTED INTERNALLY. FOR
INCREASED RELIABILITY OF THE SOLDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PAD BE SOLDERED TO THE SUBSTRATE, VSS.
Figure 5. Pin Configuration
Table 9. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
D1
Drain Terminal 1. This pin can be an input or output.
2
S1
Source Terminal 1. This pin can be an input or output.
3
VSS
Most Negative Power Supply Potential. In single-supply applications, tie this pin to ground.
4, 11
GND
Ground (0 V) Reference.
5
S4
Source Terminal 4. This pin can be an input or output.
6
D4
Drain Terminal 4. This pin can be an input or output.
7, 8, 10, 12,
16, 19, 24
NIC
Not Internally Connected.
9
RESET/VL
RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V to 5.5 V supply.
Pull the RESET pin low to complete a hardware reset. After a reset, all switches open, and the appropriate registers
are set to their default.
13
D3
Drain Terminal 3. This pin can be an input or output.
14
S3
Source Terminal 3. This pin can be an input or output.
15
VDD
Most Positive Power Supply Potential.
17
S2
Source Terminal 2. This pin can be an input or output.
18
D2
Drain Terminal 2. This pin can be an input or output.
20
SDO
Serial Data Output. This pin can be used for daisy chaining a number of these devices together or for reading
back the data stored in a register for diagnostic purposes. The serial data is propagated on the falling edge of
SCLK. Pull this open-drain output to VL with an external resistor.
21
CS
Active Low Control Input. CS is the frame synchronization signal for the input data.
22
SCLK
Serial Clock Input. Data is captured on the positive edge of SCLK. Data can be transferred at rates of up to 50 MHz.
23
SDI
Serial Data Input. Data is captured on the positive edge of the serial clock input.
EPAD
Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints and
maximum thermal capability, it is recommended that the exposed pad be soldered to the substrate, VSS.



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