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ADGS1412 Datasheet(PDF) 25 Page - Analog Devices

Part # ADGS1412
Description  Serially Controlled, 1.5 廓, On-Resistance, High Voltage, iCMOS, Quad SPST Switch
PDF  26 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADGS1412 Datasheet(HTML) 25 Page - Analog Devices

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ADGS1412
Data Sheet
Rev. 0 | Page 24 of 25
ERROR FLAGS REGISTER
Address: 0x03, Reset: 0x00, Name: ERR_FLAGS
The error flags register allows the user to determine if an error has occurred. To clear the error flags register, write the special 16-bit SPI
command 0x6CA9 to the device. This SPI command does not trigger the invalid R/W address error. When CRC is enabled, the user must
include the correct CRC byte during the SPI write for the clear error flags register command to succeed.
Table 14. Bit Descriptions for ERR_FLAGS
Bits
Bit Name
Settings
Description
Default
Access
[7:3]
Reserved
These bits are reserved and are set to 0.
0x0
R
2
RW_ERR_FLAG
Error flag for invalid read/write address. The error flag asserts during a SPI
read if the target address does not exist. The error flag also asserts when
the target address of a SPI write is does not exist or is read only.
0x0
R
0
No error.
1
Error.
1
SCLK_ERR_FLAG
Error flag for the detection of the correct number of SCLK cycles in a SPI
frame.
0x0
R
0
No error.
1
Error.
0
CRC_ERR_FLAG
Error flag that determines if a CRC error has occurred during a register
write.
0x0
R
0
No error.
1
Error.
BURST ENABLE REGISTER
Address: 0x05, Reset: 0x00, Name: BURST_EN
The burst enable register allows the user to enable or disable burst mode. When enabled, the user can send multiple consecutive SPI
commands without deasserting CS.
Table 15. Bit Descriptions for BURST_EN
Bits
Bit Name
Settings
Description
Default
Access
[7:1]
Reserved
These bits are reserved; set these bits to 0.
0x0
R
0
BURST_MODE_EN
Burst mode enable bit.
0x0
R/W
0
Disabled.
1
Enabled.
SOFTWARE RESET REGISTER
Address: 0x0B, Reset: 0x00, Name: SOFT_RESETB
Use the software reset register to perform a software reset. Consecutively, write 0xA3 followed by 0x05 to this register, and the registers of
the device reset to their default state.
Table 16. Bit Descriptions for SOFT_RESETB
Bits
Bit Name
Settings
Description
Default
Access
[7:0]
SOFT_RESETB
To perform a software reset, consecutively write 0xA3 followed by 0x05 to
this register.
0x0
R



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