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MB91F464HB Datasheet(PDF) 39 Page - Cypress Semiconductor |
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MB91F464HB Datasheet(HTML) 39 Page - Cypress Semiconductor |
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39 / 105 page ![]() Document Number: 002-04621 Rev. *A Page 39 of 105 MB91460H Series 9.4.2 Pin connections in parallel programming mode Resetting after setting the MD[2:0] pins to [111] will halt CPU functioning. At this time, the Flash memory's interface circuit enables direct control of the Flash memory unit from external pins by directly linking some of the signals to GP-Ports. Please see table below for signal mapping. In this mode, the Flash memory appears to the external pins as a stand-alone unit. This mode is generally set when writing/erasing using the parallel Flash programmer. In this mode, all operations of the 8.5 Mbits Flash memory's Auto Algorithms are available. Correspondence between MBM29LV400TC and Flash Memory Control Signals 9.5 Poweron Sequence in parallel programming mode The flash memory can be accessed in programming mode after a certain wait time, which is needed for Security Vector fetch: • Minimum wait time after VDD5/VDD5R power on: 2.76 ms • Minimum wait time after INITX rising: 1.0 ms MBM29LV400TC External pins FR-CPU mode MB91F464HB external pins Comment Flash memory mode Normal function Pin number - INITX - INITX 84 RESET - FRSTX GP16_6 70 - - MD2 MD2 76 Set to ‘1’ - - MD1 MD1 75 Set to ‘1’ - - MD0 MD0 74 Set to ‘1’ RY/BY FMCS:RDY bit RY/BYX GP18_2 100 BYTE Internally fixed to ‘H’ BYTEX GP16_4 68 WE Internal control signal + control via interface circuit WEX GP16_7 71 OE OEX GP07_7 3 CE CEX GP07_6 2 - ATDIN GP18_6 103 Set to ‘0’ - EQIN GP18_5 102 Set to ‘0’ - TESTX GP16_5 69 Set to ‘1’ - RDYI GP18_4 101 Set to ‘0’ A-1 Internal address bus FA0 GP05_5 17 Set to ‘0’ A0 to A3 FA1 to FA4 GP19_0 to GP19_2, GP19_4 92 to 95 A4 to A7 FA5 to FA8 GP19_5 to GP19_6, GP18_0 to GP18_1 96 to 99 A8 to A11 FA9 to FA12 GP06_0 to GP06_3 4 to 7 A12 to A15 FA13 to FA16 GP06_4 to GP06_7 8 to 11 A16 to A18 FA17 to FA19 GP05_0 to GP05_2 12 to 14 A19 FA20 GP05_3 15 Set to ‘1’ DQ0 to DQ7 Internal data bus DQ0 to DQ7 GP00_0 to GP00_7 28 to 35 DQ8 to DQ15 DQ8 to DQ15 GP01_0 to GP01_7 20 to 27 |
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