ACT8946A datasheet(28/37 Pages) ACTIVE-SEMI

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ACT8946AQJ203-T

Rev 1.0, 08-Jul-16

ActivePMU and ActivePath are trademarks of Active-Semi.

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Table 5: REGx/DELAY[ ] Turn-On Delay

Operating Mode

REG1, REG2, and REG3 each operate in fixed-

frequency PWM mode at medium to heavy loads

when MODE[ ] bit is set to 0, and transition to a

proprietary power-saving mode at light loads in

order

maximize

standby battery

life.

applications where low noise is critical, force fixed-

frequency PWM operation across the entire load

current range, at the expense of light-load

efficiency, by setting the MODE[ ] bit to 1.

OK[ ] and Output Fault Interrupt

Each DC/DC features a power-OK status bit that

can be read by the system microprocessor via the

I2C interface. If an output voltage is lower than the

power-OK threshold, typically 7% below the

programmed regulation voltage, that regulator's

OK[ ] bit will be 0.

If a DC/DC's nFLTMSK[-] bit is set to 1, the

ACT8946A will interrupt the processor if that

DC/DC's output voltage falls below the power-OK

threshold. In this case, nIRQ will assert low and

remain asserted until either the regulator is turned

off or back in regulation, and the OK[ ] bit has been

read via I2C.

PCB Layout Considerations

High switching frequencies and large peak currents

make PC board layout an important part of step-

down DC/DC converter design. A good design

minimizes excessive EMI on the feedback paths

and voltage gradients in the ground plane, both of

which can result in instability or regulation errors.

Step-down DC/DCs exhibit discontinuous input

current, so the input capacitors should be placed as

close as possible to the IC, and avoiding the use of

via if possible. The inductor, input filter capacitor,

and output filter capacitor should be connected as

close together as possible, with short, direct, and

wide traces. The ground nodes for each regulator's

power loop should be connected at a single point in

a star-ground configuration, and this point should

be connected to the backside ground plane with

multiple via. The output node for each regulator

should be connected to its corresponding OUTx pin

through the shortest possible route, while keeping

sufficient distance from switching nodes to prevent

noise injection. Finally, the exposed pad should be

directly connected to the backside ground plane

using multiple via to achieve low electrical and

thermal resistance.

REGx/VSET[2:0]

REGx/VSET[5:3]

000

001

010

011

100

101

110

111

000

0.600

0.800

1.000

1.200

1.600

2.000

2.400

3.200

001

0.625

0.825

1.025

1.250

1.650

2.050

2.500

3.300

010

0.650

0.850

1.050

1.300

1.700

2.100

2.600

3.400

011

0.675

0.875

1.075

1.350

1.750

2.150

2.700

3.500

100

0.700

0.900

1.100

1.400

1.800

2.200

2.800

3.600

101

0.725

0.925

1.125

1.450

1.850

2.250

2.900

3.700

110

0.750

0.950

1.150

1.500

1.900

2.300

3.000

3.800

111

0.775

0.975

1.175

1.550

1.950

2.350

3.100

3.900

Table 4: REGx/VSET[ ] Output Voltage Setting

DELAY[2] DELAY[1] DELAY[0] TURN-ON DELAY

0 ms

2 ms

4 ms

8 ms

16 ms

32 ms

64 ms

128 ms

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