MPC9230

TIMING SOLUTIONS

10

MOTOROLA

Figure 4. Serial Interface Timing Diagram

Power Supply Filtering

The MPC9230 is a mixed analog/digital product. Its analog

circuitry is naturally susceptible to random noise, especially if

this noise is seen on the power supply pins. Random noise on

MPC9230 provides separate power supplies for the digital

purpose of this design technique is to try and isolate the high

switching noise digital outputs from the relatively sensitive

internal analog phase-locked loop. In a controlled environment

such as an evaluation board, this level of isolation is sufficient.

However, in a digital system environment where it is more

difficult to minimize noise on the power supplies a second level

of isolation may be required. The simplest form of isolation is a

MPC9230 is most susceptible to noise with spectral content in

the 1 kHz to 1 MHz range. Therefore, the filter should be

designed to target this range. The key parameter that needs to

be met in the final filter design is the DC voltage drop that will

assuming that a minimum of 2.835 V must be maintained on the

resistance of 10–15

Ω to meet the voltage drop criteria. The RC

filter pictured will provide a broadband filter with approximately

100:1 attenuation for noise whose spectral content is above

20 kHz. As the noise frequency crosses the series resonant

point of an individual capacitor its overall impedance begins to

look inductive and thus increases with increasing frequency.

The parallel capacitor combination shown ensures that a low

impedance path to ground exists for frequencies well above the

bandwidth of the PLL. Generally, the resistor/capacitor filter will

be cheaper, easier to implement and provide an adequate level

of supply filtering. A higher level of attenuation can be achieved

by replacing the resistor with an appropriate valued inductor. A

1000

µH choke will show a significant impedance at 10 kHz

frequencies and above. Because of the current draw and the

resistance inductor is required (less than 15

Ω).

Layout Recommendations

The MPC9230 provides sub-nanosecond output edge rates

and thus a good power supply bypassing scheme is a must.

MPC9230. There exists many different potential board layouts

and the one pictured is but one. The important aspect of the

quality general purpose chip capacitors with good PCB layout

techniques will produce effective capacitor resonances at

frequencies adequate to supply the instantaneous switching

current for the MPC9230 outputs. It is imperative that low

inductance chip capacitors are used; it is equally important that

the board layout does not introduce back all of the inductance

saved by using the leadless capacitors. Thin interconnect

traces between the capacitor and the power plane should be

avoided and multiple large vias should be used to tie the

capacitors to the buried power planes. Fat interconnect and

large vias will help to minimize layout induced inductance and

thus maximize the series resonant point of the bypass

capacitors. Note the dotted lines circling the crystal oscillator

connection to the device. The oscillator is a series resonant

circuit and the voltage amplitude across the crystal is relatively

small. It is imperative that no actively switching signals cross

under the crystal as crosstalk energy coupled to these lines

could significantly impact the jitter of the device. Special

attention should be paid to the layout of the crystal to ensure a

stable, jitter free interface between the crystal and the on-board

oscillator. Although the MPC9230 has several design features

to minimize the susceptibility to power supply noise (isolated

S_CLOCK

S_DATA

S_LOAD

M[8:0]

N[1:0]

P_LOAD

T2 T1

T0

N1

N0

M8

M7

M6

M5

M4

M3

M2

M1

M0

M, N

First

Bit

Last

Bit

MPC9230

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com