ADT7516 datasheet(6/44 Pages) AD

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ADT7516/ADT7517/ADT7519

Rev. A | Page 6 of 44

Parameter1

Min

Typ

Max

Unit

Conditions/Comments

POWER REQUIREMENTS

VDD

2.7

5.5

VDD Settling Time

VDD settles to within 10% of its final voltage level.

IDD (Normal Mode)11

VDD = 3.3 V, VIH = VDD, and VIL = GND.

2.2

VDD = 5 V, VIH = VDD, and VIL = GND.

IDD (Power-Down Mode)

µA

VDD = 3.3 V, VIH = VDD, and VIL = GND.

µA

VDD = 5 V, VIH = VDD, and VIL = GND.

Power Dissipation

VDD = 3.3 V. Normal mode.

µW

VDD = 3.3 V. Shutdown mode.

1 See the

section.

Terminology

2 DC specifications are tested with the outputs unloaded.

3 Linearity is tested using a reduced code range: ADT7516 (Code 115 to 4095); ADT7517 (Code 28 to 1023); ADT7519 (Code 8 to 255).

4 Guaranteed by design and characterization, not production tested.

5 Round robin is the continuous sequential measurement of the following channels: VDD, internal temperature, external temperature (AIN1, AIN2), AIN3, and AIN4.

6 For the amplifier output to reach its minimum voltage, the offset error must be negative. For the amplifier output to reach its maximum voltage (VREF = VDD), the offset

plus gain error must be positive.

7 The SDA and SCL timing is measured with the input filters turned on to meet the fast-mode I2C specification. Switching off the input filters improves the transfer rate

but has a negative effect on the EMC behavior of the part.

8 Guaranteed by design, not production tested.

9 All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD), and timed from a voltage level of 1.6 V.

10 Measured with the load circuit shown in Figure 4.

11 The IDD specification is valid for all DAC codes and full-scale analog input voltages. Interface inactive. All DACs and ADCs active. Load currents excluded.

DAC AC CHARACTERISTICS

Table 2. VDD = 2.7 V to 5.5 V, RL = 4.7 kΩ to GND; CL = 200 pF to GND; 4.7 kΩ to VDD; all specifications TMIN to TMAX, unless

otherwise noted.

Parameter1, 2

Min

Typ3

Max

Unit

Conditions/Comments

Output Voltage Settling Time

VREF = VDD = 5 V.

ADT7519

µs

1/4 scale to 3/4 scale change (40h to C0h).

ADT7517

µs

1/4 scale to 3/4 scale change (100h to 300h).

ADT7516

µs

1/4 scale to 3/4 scale change (400h to C00h).

Slew Rate

0.7

V/µs

Major-Code Change Glitch Energy

nV-s

1 LSB change around major carry.

Digital Feedthrough

0.5

nV-s

Digital Crosstalk

nV-s

Analog Crosstalk

0.5

nV-s

DAC-to-DAC Crosstalk

nV-s

Multiplying Bandwidth

200

kHz

VREF = 2 V ±0.1 V p-p.

Total Harmonic Distortion

–70

VREF = 2.5 V ±0.1 V p-p. Frequency = 10 kHz.

1 See

section.

Terminology

2 Guaranteed by design and characterization, not production tested.

3 @ 25°C.

SCL

SDA

DATA IN

SDA

DATA OUT

Figure 2. I2C Bus Timing Diagram

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