Note 13: The doubler section is tested at 1.89 GHz, and it is guaranteed by design to operate within 1.7 — 1.9 GHz range.

Note 15: Tested in a 50

Ω environment.

AC Timing Characteristics

Serial Data Input Timing

TEST CONDITIONS: The Serial Data Input Timing is tested using a symmetrical waveform around V

an skew rate of 0.6V/ns.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

t

CS

Data to Clock Set Up Time

Refer to Test Condition.

50

—

—

ns

t

CH

Data to Clock Hold Time

Refer to Test Condition.

10

—

—

ns

t

CWH

Clock Pulse Width High

Refer to Test Condition.

50

—

—

ns

t

CWL

Clock Pulse Width Low

Refer to Test Condition.

50

—

—

ns

t

ES

Clock to Load Enable Set Up Time

Refer to Test Condition.

50

—

—

ns

t

EW

Load Enable Pulse Width

Refer to Test Condition.

50

—

—

ns

DS012815-3

Notes: Parenthesis data indicates programmable reference divider data.

Data shifted into register on clock rising edge.

Data is shifted in MSB first.

www.national.com

7