MLX90367

Triaxis

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MLX90367

Page 20 of 36

Datasheet

Rev 5.2

Dec. 15, 15

14.4. Start-up

During the chip initialization, the output remains high until the circuit emits four initialization frames (all 6

data nibble zero). The fifth frame is not an initialization frame but a valid frame containing a measured

angle. See also section 9 “Timing specifications”. The first four frames conform to the SENT specification

and include a valid CRC.

14.5. Field sensing (A2D conversions) and the frame Synchro pulse

By default setting of the Timer period and Filter =1, the digital angle (fast channel payload) results of the

average of two angles.

These angles are themselves computed from 4 ADCs values.

The time between the ADCs and the frame synchro pulse is constant.

As a result, the phase delay between the magnetic field angle and the SENT synchro pulse is constant,

allowing filtering at the ECU side.

See also section 9 “Timing specifications”.