ADF4007

Rev. 0 | Page 10 of 16

MUXOUT

The output multiplexer on the ADF4007 allows the user to

access various internal points on the chip. The state of

MUXOUT is controlled by the M2 and M1 pins. Figure 12

shows the MUXOUT section in block diagram form.

DGND

CONTROL

MUX

R COUNTER OUTPUT

N COUNTER OUTPUT

DGND

MUXOUT

Figure 12. MUXOUT Circuit

PFD Polarity

The PFD polarity is set by the state of M2 and M1 pins as given

in the Table 5. The ability to set the polarity allows the use of

VCOs with either positive or negative tuning characteristics. For

standard VCOs with positive characteristics (output frequency

increases with increasing tuning voltage), the polarity should be

set to positive. This is accomplished by tying M2 and M1 to a

logic low state.

CP Output

The CP output state is also controlled by the state of M2 and

M1. It can be set either to active (so that the loop can be locked)

or to three-state (open the loop). The normal state is CP output

active.