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LIS2HH12 Datasheet(PDF) 32 Page - STMicroelectronics |
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LIS2HH12 Datasheet(HTML) 32 Page - STMicroelectronics |
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32 / 47 page  Register description LIS2HH12 32/47 DocID025344 Rev 5 ODR [2:0] is used to set the power mode and ODR selection. The following table lists the bit settings for power-down mode and each available frequency. The BDU bit is used to inhibit the update of the output registers until both upper and lower register parts are read. In default mode (BDU = ‘0’) the output register values are updated continuously. When the BDU is activated (BDU = ‘1’), the content of the output registers is not updated until both MSB and LSB are read which avoids reading values related to different sample times. Table 24. ODR register setting ODR2 ODR1 ODR0 Power-down and ODR selection 0 0 0 Power-down 0 0 1 10 Hz 0 1 0 50 Hz 0 1 1 100 Hz 1 0 0 200 Hz 1 0 1 400 Hz 1 1 0 800 Hz 1 1 1 N.A. Table 25. Low-pass cutoff frequency in high resolution mode (HR = 1) HR CTRL2 (DFC [1:0]) LP cutoff freq. [Hz] 1 00 ODR/50 1 01 ODR/100 1 10 ODR/9 1 11 ODR/400 |
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