AFE5804ZCF datasheet(51/63 Pages) TI1

51 / 63 page

Attenuator

8kW

7pF

0.1mF

0.1 F

(+2.4V)

T/R

AFE5804

www.ti.com

SBOS442C

– JUNE 2008 – REVISED OCTOBER 2011

APPLICATION INFORMATION

The

LNA

closed-loop

architecture

internally

ANALOG INPUT AND LNA

compensated for maximum stability without the need

for external compensation components (inductors or

While the LNA is designed as a fully differential

capacitors). At the same time, the total input

amplifier, it is optimized to perform a single-ended

capacitance is kept to a minimum with only 16pF.

input to differential output conversion. A simplified

This architecture minimizes any loading of the signal

schematic of an LNA channel is shown in Figure 101.

source

that

may

otherwise

lead

A bias voltage (VB) of +2.4V is internally applied to

frequency-dependent voltage divider. Moreover, the

the LNA inputs through 8k

Ω resistors. In addition, the

closed-loop design yields very low offsets and offset

dedicated signal input (IN pin) includes a pair of

drift; this consideration is important because the LNA

back-to-back diodes that provide a coarse input

directly drives the subsequent voltage-controlled

clamping function in case the input signal rises to

attenuator.

very

large

levels,

exceeding

0.6VPP.

This

configuration prevents the LNA from being driven into

The LNA of the AFE5804 uses the benefits of a

a severe overload state, which may otherwise cause

bipolar

process

technology

achieve

an extended overload recovery time. The integrated

exceptionally low noise voltage of 0.75nV/

√Hz, and a

diodes are designed to handle a dc current of up to

low current noise of only 3pA/

√Hz (in TGC mode 1).

approximately 5mA. Depending on the application

With these input-referred noise specifications, the

requirements, the system overload characteristics

AFE5804 achieves very low noise figure numbers

may be improved by adding external Schottky diodes

over a wide range of source resistances and

at the LNA input, as shown in Figure 101.

frequencies

(see

the

graph,

Noise

Figure

Frequency Over RS in the Typical Characteristics).

As Figure 101 also shows, the complementary LNA

The optimal noise power matching is achieved for

input (VBL pin) is internally decoupled by a small

source impedances of around 200

Ω. Further details

capacitor. Furthermore, for each input channel, a

of the AFE5804 input noise performance are shown

separate

VBL pin is brought out for external

in the Typical Characteristic graphs.

bypassing. This bypassing should be done with a

small, 0.1

μF (typical) ceramic capacitor placed in

Table 18. Noise Figure versus

close proximity to each VBL pin. Attention should be

Source Resistance (RS) at 2MHz

given to provide a low-noise analog ground for this

bypass capacitor. A noisy ground potential may

RS (Ω)

NOISE FIGURE (dB)

cause noise to be picked up and injected into the

2.1

signal path, leading to higher noise levels.

200

1.1

400

1.2

1000

1.9

Figure 101. LNA Channel (Simplified Schematic)

AFE5804ZCF Datasheet(PDF) 51 Page - Texas Instruments

AFE5804ZCF Datasheet(HTML) 51 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Datasheet Download

Link URL