PC97307 datasheet(122/218 Pages) NSC

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Parallel Port (Logical Device 4)

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Bit 7 -Printer Status

This bit reflects the inverse of the state of the BUSY sig-

nal.

0 - Printer is busy (cannot accept another character

now).

1 - Printer not busy (ready for another character).

6.5.6

ECP Control Register (DCR), Offset 002h

Reading this register returns the register content (not the

signal values, as in SPP mode).

FIGURE 6-20. DCR Register Bitmap

Bit 0 - Data Strobe Control

Bit 0 directly controls the data strobe signal to the printer

via the STB signal. It is the inverse of the STB signal.

0 - The STB signal is inactive in all modes except 010

and 011. In these modes, it may be active or inac-

tive as set by the software.

1 - In all modes, STB is active.

Bit 1 - Automatic Line Feed Control

This bit directly controls the automatic feed XT signal to

the printer via the AFD signal. Setting this bit high caus-

es the printer to automatically feed after each line is

printed. This bit is the inverse of the AFD signal.

In mode 011, AFD is activated by both ECP hardware

and by software using this bit.

0 - No automatic line feed. (Default)

1 - Automatic line feed.

Bit 2 - Printer Initialization Control

Bit 2 directly controls the signal to initialize the printer via

the INIT signal. Setting this bit to low initializes the print-

er. The INIT signal follows this bit.

0 - Initialize printer. (Default)

1 - Printer initialized.

Bit 3 - Parallel Port Input Control

This bit directly controls the select input device signal to

the printer via the SLIN signal. It is the inverse of the

SLIN signal.

This bit must be set to 1 before enabling the EPP or

ECP modes.

0 - The printer is not selected.

1 - The printer is selected.

76543210

Reset

Required

ECP Control

Offset 002h

Printer Initialization Control

Interrupt Enable

Direction Control

Reserved

Data Strobe Control

Automatic Line Feed Control

Parallel Port Input Control

Bit 4 - Interrupt Enable

Bit 4 enables the interrupt generated by the ACK signal.

In ECP mode, this bit should be set to 0. This bit does

not float the IRQ pin.

0 - Masked. (Default)

1 - Enabled.

Bit 5 - Direction Control

This bit determines the direction of the parallel port.

This is a read/write bit in EPP mode. In SPP mode it is

a write only bit. A read from it returns 1. In SPP Compat-

ible mode and in EPP mode it does not control the direc-

tion. See Table 6-4.

The ECP drives the PD7-0 pins in the forward direction,

but does not drive them in the backward direction.

This bit is readable and writable. In modes 000 and 010

the direction bit is forced to 0, internally, regardless of

the data written into this bit.

0 - ECP drives forward in output mode. (Default)

1 - ECP direction is backward.

Bits 7,6 - Reserved

These bits are reserved and are always 1.

6.5.7

Parallel Port Data FIFO (CFIFO) Register,

Bits 7-5 of ECR = 010, Offset 400h

The Parallel Port FIFO (CFIFO) register is write only. A byte

written to this register by PIO or DMA is pushed into the

FIFO and tagged as data.

Reading this register has no effect and the data read is un-

defined.

FIGURE 6-21. CFIFO Register Bitmap

6.5.8

ECP Data FIFO (DFIFO) Register,

Bits 7-5 of ECR = 011, Offset 400h

This bi-directional FIFO functions as either a write-only de-

vice when bit 5 of DCR is 0, or a read-only device when it is

In the forward direction (bit 5 of DCR is 0), a byte written to

the ECP Data FIFO (DFIFO) register by PIO or DMA is

pushed into the FIFO and tagged as data. Reading this reg-

ister when set for write-only has no effect and the data read

is undefined.

In the backward direction (bit 5 of DCR is 1), the ECP auto-

matically issues ECP read cycles to fill the FIFO.

Reset

Required

Parallel Port FIFO

Offset 400h

Bits 7-5 of ECR = 010

76543210

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