PC87570-ICCSLASHVUL datasheet(122/168 Pages) NSC

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Analog to Digital Converter (ADC) - January 1998

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16.3 OPERATION MODES

The ADC supports four modes of automated operation, as

defined by SCAN and CONT of the ADCCNT2 Register. Ta-

ble 16-3 summarizes ADC operation in the various modes.

Channel and mode selection (CHANNEL, SCAN and CONT

of the ADCCNT2 Register) should be changed only when

no conversion is in progress (i.e., START of the ADCCNT2

In the scan modes, CHANNEL points to the first channel to

be converted. The other three channels use a modulo-8

counting scheme (channel 7 is followed by channel 0).

Table 16-3. ADC Operation Modes

Mode

ADCCNT2

Description

SCAN CONT

One

Channel,

Single

Conversion

One conversion is performed for the channel speciﬁed by CHANNEL of the ADCCNT2

The result is placed in the ADDATA0 Register.

START of the ADCCNT2 Register is cleared.

EOC of the ADCST Register is set.

The interrupt request signal is asserted (1) if INTE of the ADCCNT1 Register is set.

One

Channel,

Continuous

Conversion

Continuous conversions are performed for the channel speciﬁed by CHANNEL of the

ADCCNT2 Register. The next conversion starts only after a pause deﬁned by DELAY of the

ADCCNT3 Register. The hardware does not clear START of the ADCCNT2 Register.

When a conversion is completed:

The consecutive results are placed in the four data registers cyclically, starting from

ADDATA0.

The last conversion result is pointed to by BUFPTR of the ADCST Register.

When all the four data registers are loaded, EOC of the ADCST Register is set.

If interrupts are enabled (INTE of the ADCCNT1 Register is set), an interrupt is issued to

the ICU.

Repetitive conversions are started until START of the ADCCNT2 Register is cleared by the

software. When this occurs:

Any currently executing conversion is completed.

EOC of the ADCST Register is set.

No new conversion is started.

The last conversion result is pointed to by BUFPTR of the ADCST Register.

Four

Channel

Scan,

Single

Conversion

A conversion is performed for four channels, starting with the channel deﬁned in CHANNEL of

the ADCCNT2 Register. After completion of each conversion, the selector of the input

multiplexer is incremented. Conversion for the next channel is started after the sampling time

delay, deﬁned by DELAY of the ADCCNT3 Register. The conversion stops after all four

channels are converted.

The following procedure is implemented:

The results are placed in the ADDATA0-3 Registers for channels 1-4, respectively.

When all four channels have been converted, START of the ADCCNT2 Register is cleared

by hardware, and EOC of the ADCST Register is set.

If INTE of the ADCCNT1 Register is set, an interrupt is issued.

Four

Channel

Scan,

Continuous

Conversion

Conversion of the selected four channels is continuously repeated. Each conversion cycle is

performed as in “Four Channel Scan, Single Conversion” mode, but the hardware does not

clear START of the ADCCNT2 Register.

When a conversion cycle is completed and if START is still set, a new four channel conversion

cycle is started. When the conversion of all four channels is completed:

START is not cleared.

EOC is set.

The interrupt signal is asserted if INTE=1.

Repetitive conversion cycles are started until the START bit is cleared by software. When this

PC87570-ICC/VUL Datasheet(PDF) 122 Page - National Semiconductor (TI)

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