PC87570-ICCSLASHVUL datasheet(99/168 Pages) NSC

99 / 168 page

ACCESS.bus (ACB) Interface

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down the SDA line during the acknowledge clock pulse,

thus signalling the correct reception of the last data byte,

and its readiness to receive the next byte. Figure 13-4 illus-

trates the acknowledge cycle.

13.2.5

“Acknowledge after every byte” Rule

The master generates an acknowledge clock pulse after

each byte transfer. The receiver sends an acknowledge sig-

nal after every byte received.

There are two exceptions to the “acknowledge after every

byte” rule.

1. When the master is the receiver, it must indicate to the

transmitter an end of data by not-acknowledging (“neg-

ative acknowledge”) the last byte clocked out of the

slave. This “negative acknowledge” still includes the ac-

knowledge clock pulse (generated by the master), but

the SDA line is not pulled down.

2. When the receiver is full, otherwise occupied, or a prob-

Start

Condition

Stop

Condition

SDA

SCL

MSB

ACK

12 3 - 6

3 - 8

Acknowledgment

Signal From Receiver

Byte Complete

Interrupt Within

Receiver

Clock Line Held

Low by Receiver

While Interrupt

is Serviced

Figure 13-3. ACCESS.bus Data Transaction

Start

Condition

SCL

12 3 - 6

Transmitter Stays Off the

Bus During the

Acknowledge Clock

Acknowledge

Signal from Receiver

Figure 13-4. ACCESS.bus Acknowledge Cycle

Data Output

Transmitter

Data Output

Receiver

Start

Condition

Stop

Condition

SDA

SCL

1 - 7

Address R/W ACK

Data

ACK

Data

ACK

Figure 13-5. A Complete ACCESS.bus Data Transaction

PC87570-ICC/VUL Datasheet(PDF) 99 Page - National Semiconductor (TI)

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