DM368ZCEZ datasheet(64/208 Pages) TI1

64 / 208 page

TMS320DM368

SPRS668C

– APRIL 2010 – REVISED JUNE 2011

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3.6

Device Reset

There are five types of reset. The types of reset differ by how they are initiated and/or by their effect on

the chip. Each type is briefly described in Table 3-11 and further described in the TMS320DM36x DMSoC

ARM Subsystem Reference Guide (literature number SPRUFG5).

Table 3-11. Reset Types

Type

Initiator

Effect

POR (Power-On-Reset)

RESET pin low and TRST low

Total reset of the chip (cold reset).

Activates the POR signal on chip, which is used to reset

test/emulation logic.

Warm Reset

RESET pin low

Resets everything except for test/emulation logic.

ARM emulator stays alive during Warm reset.

Max Reset

ARM emulator or Watchdog Timer

Same effect as warm reset.

(WDT)

System Reset

ARM emulator

A soft reset.

Soft reset maintains memory contents, and does not affect or reset

clocks or power states.

Module Reset

ARM software

Can independently apply reset to each module, via an MMR.

Intended as a debug tool, and not necessarily for general use.

3.7

Default Device Configurations

After POR, warm reset, and max reset, the chip is in its default configuration. This section highlights the

default configurations associated with PLLs, clocks, ARM boot mode, and AEMIF.

Note: Default configuration is the configuration immediately after POR, warm reset, and max reset and

just before the boot process begins. The boot ROM updates the configuration. See Section 3.2 for more

information on the boot process.

3.7.1

Device Configuration Pins

The device configuration pins are described in Table 3-12. The device configuration pins are latched at

reset and allow you to configure all of the following options at reset:

•

ARM Boot Mode

•

Asynchronous EMIF pin configuration

These pins are described further in the following sections.

Note: The device configuration pins are multiplexed with AEMIF pins. After the device configuration pins

are sampled at reset, they automatically change to function as AEMIF pins. Pin multiplexing is described

in Section 3.5.

Table 3-12. Device Configuration

Default Setting (by internal

Sampled

pull-up/

Device Configuration Input

Function

pull-down)

BTSEL[2:0]

Selects ARM boot mode

EM_A[13:11]

000

000 = Boot from ROM (NAND)

(Boot from ROM - NAND)

001 = Boot from AEMIF

010 = Boot from ROM (MMC/SD)

011 = Boot from ROM (UART)

100 = Boot from ROM (USB)

101 = Boot from ROM (SPI)

110 = Boot from ROM (EMAC)

111 = Boot from ROM (HPI)

AECFG[2:0]

AEMIF Configuration(1)

EM_A[10:8]

000

AECFG[2] = '0' for 8-bit AEMIF configuration

(8-bit NAND)

AECFG[2] = '1' for 16-bit AEMIF configuration

(1)

Other supported AECFG[2:0] combinations can be found in Table 3-14.

Device Configurations

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