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DM368ZCEZ Datasheet(PDF) 1 Page - Texas Instruments |
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DM368ZCEZ Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 208 page  TMS320DM368 www.ti.com SPRS668C – APRIL 2010 – REVISED JUNE 2011 TMS320DM368 Digital Media System-on-Chip (DMSoC) Check for Samples: TMS320DM368 1 TMS320DM368 Digital Media System-on-Chip (DMSoC) 1.1 Features 12 device • Highlights • ARM926EJ-S™ Core – High-Performance Digital Media System-on-Chip (DMSoC) – Support for 32-Bit and 16-Bit (Thumb ® Mode) Instruction Sets – 432-MHz ARM926EJ-S Clock Rate – DSP Instruction Extensions and Single Cycle – Two Video Image Co-processors MAC (HDVICP, MJCP) Engines – ARM® Jazelle® Technology – Supports a Range of Encode, Decode, and Video Quality Operations – Embedded ICE-RT Logic for Real-Time Debug – Video Processing Subsystem • ARM9 Memory Architecture • HW Face Detect Engine – 16K-Byte Instruction Cache • Resize Engine from 1/16x to 8x – 8K-Byte Data Cache • 16-Bit Parallel AFE (Analog Front-End) Interface Up to 120 MHz – 32K-Byte RAM • 4:2:2 (8-/16-bit) Interface – 16K-Byte ROM • 8-/16-bit YCC and Up to 24-Bit RGB888 – Little Endian Digital Output • Two Video Image Co-processors • 3 DACs for HD Analog Video Output (HDVICP, MJCP) Engines • Hardware On-Screen Display (OSD) – Support a Range of Encode and Decode Operations – Capable of 1080p 30fps H.264 video processing – H.264, MPEG4, MPEG2, MJPEG, JPEG, WMV9/VC1 – Peripherals include EMAC, USB 2.0 OTG, DDR2/NAND, 5 SPIs, 2 UARTs, 2 • Video Processing Subsystem MMC/SD/SDIO, Key Scan – Front End Provides: – 8 Different Boot Modes and Configurable • HW Face Detect Engine Power-Saving Modes • Hardware IPIPE for Real-Time Image – Pin-to-pin and software compatible with Processing DM365 – Resize Engine – Extended temperature (-40ºC – 85ºC) – Resize Images From 1/16x to 8x available – Separate Horizontal/Vertical – 3.3-V and 1.8-V I/O, 1.35-V Core Control – 338-Pin Ball Grid Array at 65nm Process – Two Simultaneous Output Paths Technology • IPIPE Interface (IPIPEIF) • High-Performance Digital Media • Image Sensor Interface (ISIF) and CMOS System-on-Chip (DMSoC) Imager Interface – 432-MHz ARM926EJ-S Clock Rate • 16-Bit Parallel AFE (Analog Front End) – 4:2:2 (8-/16-Bit) Interface Interface Up to 120 MHz – Capable of 1080p 30fps H.264 video • Glueless Interface to Common Video processing Decoders – Pin compatible with DM365 processors • BT.601/BT.656/BT.1120 Digital YCbCr – Fully Software-Compatible With ARM9™ 4:2:2 (8-/16-Bit) Interface – Extended temperature available for 432-MHz • Histogram Module 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2010–2011, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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