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DM368ZCEZ Datasheet(PDF) 14 Page - Texas Instruments |
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DM368ZCEZ Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 208 page  TMS320DM368 SPRS668C – APRIL 2010 – REVISED JUNE 2011 www.ti.com 2.6 Memory Map Summary Table 2-3 shows the memory map address ranges of the device. Table 2-4 depicts the expanded map of the Configuration Space (0x01C0 0000 through 0x01FF FFFF). The device has multiple on-chip memories associated with its processor and various subsystems. To help simplify software development a unified memory map is used where possible to maintain a consistent view of device resources across all bus masters. The bus masters are the ARM, EDMA, EMAC, USB, HPI, MJCP, HDVICP and VPSS. The Master Peripherals are EMAC, USB, and HPI. Please refer to Section 4 for more details. Table 2-3. Memory Map Start Address End Address Size (Bytes) ARM EDMA Master Periph VPSS Mem Map Mem Map Mem Map Mem Map 0x0000 0000 0x0000 3FFF 16K ARM RAM0 (Instruction) 0x0000 4000 0x0000 7FFF 16K ARM RAM1 Reserved Reserved (Instruction) 0x0000 8000 0x0000 BFFF 16K ARM ROM (Instruction) 0x0000 C000 0x0000 FFFF 16K Reserved 0x0001 0000 0x0001 3FFF 16K ARM RAM0 (Data) ARM RAM0 ARM RAM0 0x0001 4000 0x0001 7FFF 16K ARM RAM1 (Data) ARM RAM1 ARM RAM1 0x0001 8000 0x0001 BFFF 16K ARM ROM ARM ROM ARM ROM 0x0001 C000 0x000F FFFF 912K Reserved 0x0010 0000 0x01BB FFFF 26M 0x01BC 0000 0x01BC 0FFF 4K ARM ETB Mem 0x01BC 1000 0x01BC 17FF 2K ARM ETB Reg Reserved 0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher Reserved 0x01BC 1900 0x01BC FFFF 59136 Reserved 0x01BD 0000 0x01BF FFFF 192K 0x01C0 0000 0x01FF FFFF 4M CFG Bus CFG Bus CFG Bus Peripherals Peripherals Peripherals 0x0200 0000 0x09FF FFFF 128M ASYNC EMIF (Data) ASYNC EMIF (Data) 0x0A00 0000 0x11EF FFFF 127M - 16K Reserved Reserved 0x11F0 0000 0x11F1 FFFF 128K MJCP DMA Port MJCP DMA Port 0x11F2 0000 0x11FF FFFF 896K Reserved Reserved 0x1200 0000 0x1207 FFFF 512K HDVICP DMA Port1 HDVICP DMA Port1 HDVICP DMA Port1 0x1208 0000 0x120F FFFF 512K Reserved HDVICP DMA Port2 Reserved 0x1210 0000 0x1217 FFFF 512K HDVICP DMA Port3 0x1218 0000 0x1FFF FFFF 222.5M Reserved 0x2000 0000 0x2000 7FFF 32K DDR EMIF Control DDR EMIF Control Regs Regs 0x2000 8000 0x41FF FFFF 544M-32K 0x4200 0000 0x49FF FFFF 128M Reserved Reserved 0x4A00 0000 0x7FFF FFFF 864M 0x8000 0000 0x8FFF FFFF 256M DDR EMIF DDR EMIF DDR EMIF DDR EMIF 0x9000 0000 0xFFFF FFFF 1792M Reserved Reserved Reserved Reserved 14 Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TMS320DM368 |
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