TNETV6446AINZWT datasheet(105/227 Pages) TI1

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MXI/CLKIN

TMS320DM6446

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SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1

with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1). For the

PLL lock time value, see Table 6-15.

Table 6-15. PLL1 and PLL2 Stabilization, Lock, and Reset Times

PLL STABILIZATION/LOCK/RESET TIME

MIN

TYP

MAX

UNIT

PLL Stabilization Time

150

PLL Lock Time

2000C(1)

PLL Reset Time

128C(1)

(1)

C = CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 27 MHz, use C = 37.037 ns.

For details on the PLL initialization software sequence, see the TMS320DM644x DMSoC ARM Subsystem

Reference Guide (literature number SPRUE14).

6.6.2

Clock PLL Considerations with External Clock Sources

If the internal oscillator is bypassed, to minimize the clock jitter a single clean power supply should power

both the DM6446 device and the external clock oscillator circuit. The minimum CLKIN rise and fall times

should also be observed. For the input clock timing requirements, see Section 6.6.3, Clock PLL Electrical

Data/Timing (Input and Output Clocks).

Rise/fall times, duty cycles (high/low pulse durations), and the load capacitance of the external clock

source must meet the device requirements in this data manual (see Section 5.3, Electrical Characteristics

Over Recommended Ranges of Supply Voltage and Operating Case Temperature, and Section 6.6.3,

Clock PLL Electrical Data/Timing (Input and Output Clocks).

6.6.3

Clock PLL Electrical Data/Timing (Input and Output Clocks)

Table 6-16. Timing Requirements for MXI/CLKIN (-594) Devices(1) (2) (3) (4) (see Figure 6-14)

A-513,

-594,

NO.

UNIT

-810

MIN

MAX

tc(MXI)

Cycle time, MXI/CLKIN

33.3

tw(MXIH)

Pulse duration, MXI/CLKIN high

0.45C

0.55C

tw(MXIL)

Pulse duration, MXI/CLKIN low

0.45C

0.55C

tt(MXI)

Transition time, MXI/CLKIN

0.05C

tJ(MXI)

Period jitter, MXI/CLKIN

0.02C

(1)

The MXI/CLKIN frequency and PLL multiply factor should be chosen such that the resulting clock frequency is within the specific range

for CPU operating frequency. For example, for a -594 speed device with a 27 MHz CLKIN frequency, the PLL multiply factor should be

≤ 22. For example, for a -810 speed device with a 27 MHz CLKIN frequency, the PLL multiply factor should be ≤ 30.

(2)

The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.

(3)

For more details on the PLL multiplier factors, see the TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number

SPRUE14).

(4)

C = CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 27 MHz, use C = 37.037 ns.

Figure 6-14. MXI/CLKIN Timing

Peripheral and Electrical Specifications

105

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