TNETV6446AINZWT datasheet(14/227 Pages) TI1

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TMS320DM6446

SPRS283H – DECEMBER 2005 – REVISED SEPTEMBER 2010

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2.3.9

Peripherals

The ARM9 has access to all of the peripherals on the DM6446 device with the exception of the VICP.

2.3.10 PLL Controller (PLLC)

The ARM Subsystem includes the PLL Controller. The PLL Controller contains a set of registers for

configuring DM6446’s two internal PLLs (PLL1 and PLL2). The PLL Controller provides the following

configuration and control:

•

PLL Bypass Mode

•

Set PLL multiplier parameters

•

Set PLL divider parameters

•

PLL power down

•

Oscillator power down

The PLLs are briefly described in this document in Section 6.6, Clock PLLs. For more detailed information

on the PLLs and PLL Controller register descriptions, see the TMS320DM644x DMSoC ARM Subsystem

Reference Guide (literature number SPRUE14).

2.3.11 Power and Sleep Controller (PSC)

The ARM Subsystem includes the Power and Sleep Controller (PSC). Through register settings

accessible by the ARM9, the PSC provides two levels of power savings: peripheral/module clock gating

and power domain shut-off. Brief details on the PSC are given in Section 6.3, Power Supplies. For more

detailed information and complete register descriptions for the PSC, see the TMS320DM644x DMSoC

ARM Subsystem Reference Guide (literature number SPRUE14).

2.3.12 ARM Interrupt Controller (AINTC)

The ARM Interrupt Controller (AINTC) accepts device interrupts and maps them to either the ARM’s IRQ

(interrupt request) or FIQ (fast interrupt request). The ARM Interrupt Controller is briefly described in

Section 6.7, Interrupts, of this document. For detailed information on the ARM Interrupt Controller, see the

TMS320DM644x DMSoC ARM Subsystem Reference Guide (literature number SPRUE14).

2.3.13 System Module

The ARM Subsystem includes the System module. The System module consists of a set of registers for

configuring and controlling a variety of system functions. For details and register descriptions for the

System module, see Section 3, Device Configurations, and see the TMS320DM644x DMSoC ARM

Subsystem Reference Guide (literature number SPRUE14).

2.3.14 Power Management

DM6446 has several means of managing power consumption. There is extensive use of clock gating,

which reduces the power used by global device clocks and individual peripheral clocks. Clock

management can be utilized to reduce clock frequencies in order to reduce switching power. For more

details on power management techniques, see Section 3 (Device Configurations), Section 6 (Peripheral

and Electrical Specifications), and see the TMS320DM644x DMSoC ARM Subsystem Reference Guide

(literature number SPRUE14).

DM6446 gives the programmer full flexibility to use any and all of the previously mentioned capabilities to

customize an optimal power management strategy. Several typical power management scenarios are

described in the following sections.

Device Overview

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