TMS320VC5402 datasheet(45/72 Pages) TI1

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TMS320VC5402

FIXEDPOINT DIGITAL SIGNAL PROCESSOR

SPRS079G − OCTOBER 1998 − REVISED OCTOBER 2008

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251−1443

memory and parallel I/O interface timing (continued)

switching characteristics over recommended operating conditions for a parallel I/O port write

(IOSTRB = 0) [H = 0.5 tc(CO)]† (see Figure 16)

PARAMETER

MIN

MAX

UNIT

td(CLKL-A)

Delay time, CLKOUT low to address valid

−2

td(CLKH-ISTRBL)

Delay time, CLKOUT high to IOSTRB low

−2

td(CLKH-D)IOW

Delay time, CLKOUT high to write data valid

H−5

H+8

td(CLKH-ISTRBH)

Delay time, CLKOUT high to IOSTRB high

−2

td(CLKL-RWL)

Delay time, CLKOUT low to R/W low

−1

td(CLKL-RWH)

Delay time, CLKOUT low to R/W high

−1

th(A)IOW

Hold time, address valid after CLKOUT low

th(D)IOW

Hold time, write data after IOSTRB high

H−3

H+7

tsu(D)IOSTRBH

Setup time, write data before IOSTRB high

H−7

H+1

tsu(A)IOSTRBL

Setup time, address valid before IOSTRB low

H−2

H+2

† Address and IS timings are included in timings referenced as address.

R/W

IOSTRB

D[15:0]

A[19:0]

CLKOUT

td(CLKH-ISTRBH)

th(A)IOW

th(D)IOW

td(CLKH-D)IOW

td(CLKH-ISTRBL)

td(CLKL-A)

td(CLKL-RWL)

td(CLKL-RWH)

tsu(A)IOSTRBL

tsu(D)IOSTRBH

NOTE A: A[19:16] are always driven low during accesses to I/O space.

Figure 16. Parallel I/O Port Write (IOSTRB = 0)

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