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TNETV2501INPGF Datasheet(PDF) 180 Page - Texas Instruments |
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TNETV2501INPGF Datasheet(HTML) 180 Page - Texas Instruments |
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180 / 197 page  Electrical Specifications 180 December 2002 − Revised November 2008 SPRS206K Table 5−44. HPI Read and Write Switching Characteristics†‡§ NO. PARAMETER MIN MAX UNIT Case 1. HPIC or HPIA read 5 15 Case 2. HPID read with K = 1|| 9 * 2H + 20 Case 2. HPID read with no auto-increment¶ K = 2|| 10 * 2H + 20 no auto-increment¶ K = 4|| 11 * 2H + 20 H1 td(DSL−HDV) Delay time, DS low to HD valid Case 3. HPID read with K = 1|| 9 * 2H + 20 ns H1 td(DSL−HDV) Delay time, DS low to HD valid Case 3. HPID read with auto-increment and read FIFO initially empty¶ K = 2|| 10 * 2H + 20 ns auto-increment and read FIFO initially empty¶ K = 4|| 11 * 2H + 20 Case 4. HPID read with auto-increment and data previously prefetched into the read FIFO 5 15 H2 tdis(DSH−HDV) Disable time, HD high-impedance from DS high 1 4 ns H3 ten(DSL−HDD) Enable time, HD driven from DS low 3 15 ns H4 td(DSL−HRDYL) Delay time, DS low to HRDY low 12 ns H5 td(DSH−HRDYL) Delay time, DS high to HRDY low 12 ns Case 1. HPID read with K = 1|| 10 * 2H + 20 Case 1. HPID read with no auto-increment¶ K = 2|| 11 * 2H + 20 ns H6 td(DSL−HRDYH) Delay time, DS low to HRDY no auto-increment¶ K = 4|| 12 * 2H + 20 ns H6 td(DSL−HRDYH) Delay time, DS low to HRDY high Case 2. HPID read with K = 1|| 10 * 2H + 20 high Case 2. HPID read with auto-increment and read FIFO initially empty¶ K = 2|| 11 * 2H + 20 ns auto-increment and read FIFO initially empty¶ K = 4|| 12 * 2H + 20 ns H7 td(HDV−HRDYH) Delay time, HD valid to HRDY high 0 ns H8 td(COH−HINT) Delay time, CLKOUT high to HINT change# 8 ns Case 1. HPIA write¶ K = 1, 2, 4|| 5 * 2H + 20 H34 td(DSH-HRDYH) Delay time, DS high to HRDY Case 2. HPID write with K = 1|| 5 * 2H + 20 ns H34 td(DSH-HRDYH) Delay time, DS high to HRDY high Case 2. HPID write with no auto-increment¶ K = 2|| 5 * 2H + 20 ns no auto-increment¶ K = 4|| 6 * 2H + 20 Delay time, DS low to HRDY high for HPIA write and FIFO K = 1|| 40 * 2H + 20 H35 td(DSL-HRDYH) Delay time, DS low to HRDY high for HPIA write and FIFO not empty¶ K = 2|| 40 * 2H + 20 ns H35 td(DSL-HRDYH) not empty¶ K = 4|| 24 * 2H + 20 ns H36 td(HASL-HRDYL) Delay time, HPI.HAS low to HRDY low 12 ns † DS refers to logical OR of HCS, HDS1, and HDS2. HD refers to HPI Data Bus. HDS refers to HDS1 or HDS2. HAD refers to HCNTL0, HCNTL1, HPI.HBIL, and HR/W. ‡ H is half the SYSCLK1 clock cycle. § A host must not initiate transfer requests until the HPI has been brought out of reset, see Section 3.7, Host-Port Interface (HPI), for more details. ¶ Assumes no other DMA or CPU memory activity. # In this case, CLKOUT reflects SYSCLK1. The CLKOUT Selection Register (CLKOUTSR) can be programmed to select SYSCLK1 as CLKOUT. || K = divider ratio between CPU clock and SYSCLK1. For example, when SYSCLK1 is set to the CPU clock divided by four, use K = 4. |
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