TNETV2501INPGF datasheet(190/197 Pages) TI1

190 / 197 page

Mechanical Data

190

December 2002 − Revised November 2008

SPRS206K

Mechanical Data

Some TMX samples were shipped in the GGW package. For more information on the GGW package, see the

TMS320VC5502 and TMS320VC5501 Digital Signal Processors Silicon Errata (literature number SPRZ020D

or later).

TMS320VC5501PGF has completed Temp Cycle reliability qualification testing with no failures through

1500 cycles of −55

°C to 125°C following an EIA/JEDEC Moisture Sensitivity Level 4 pre-condition at

220+5/−0

°C peak reflow. Exceeding this peak reflow temperature condition or storage and handling

requirements may result in either immediate device failure post-reflow, due to package/die material

delamination (“popcorning”), or degraded Temp cycle life performance.

Please note that Texas Instruments (TI) also provides MSL, peak reflow and floor life information on a bar-code

label affixed to dry-pack shipping bags. Shelf life, temperature and humidity storage conditions and re-bake

instructions are prominently displayed on a nearby screen-printed label.

6.1

Package Thermal Resistance Characteristics

Table 6−1 and Table 6−2 provide the thermal resistance characteristics for the recommended package types

used on the TMS320VC5501 DSP.

NOTE:

Some TMX samples were shipped in the GGW package. For more information on the GGW

package, see the TMS320VC5502 and TMS320VC5501 Digital Signal Processors Silicon

Errata (literature number SPRZ020D or later).

Table 6−1. Thermal Resistance Characteristics (Ambient)

PACKAGE

RθJA (°C/W)

BOARD TYPE†

AIRFLOW (LFM)

High-K

150

High-K

250

(Without thermal vias)

High-K

500

(Without thermal vias)

117

Low-K

GZZ, ZZZ

114

Low-K

150

GZZ, ZZZ

109

Low-K

250

101

Low-K

500

High-K

(With thermal vias)‡

High-K

150

(With thermal vias)‡

High-K

250

High-K

500

† Board types are as defined by JEDEC. Reference JEDEC Standard JESD51−9, Test Boards for Area Array Surface Mount Package Thermal

Measurements.

‡ Adding thermal vias will significantly improve the thermal performance of the device. To use the thermal balls on the GZZ and ZZZ packages:

− An array of 25 land pads must be added on the top layer of the PCB where the package will be mounted.

− The PCB land pads should be the same diameter as the vias in the package substrate for optimal Board Level Reliability Temperature Cycle

performance.

− The land pads on the PCB should be connected together and to PCB through-holes. The PCB through-holes should in turn be connected

to the ground plane for heat dissipation.

− A solid internal plane is preferred for spreading the heat.

Refer to the MicroStar BGA

E Packaging Reference Guide (literature number SSYZ015) for guidance on PCB design, surface mount, and

reliability considerations.

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