ST72344S2 datasheet(135/247 Pages) STMICROELECTRONICS

135 / 247 page

ST72344xx, ST2345xx

On-chip peripherals

Doc ID 12321 Rev 6

135/247

Note:

Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore,

the best time to toggle the TE bit is when the TDRE bit is set, that is, before writing the next

byte in the SCIDR.

Receiver

The SCI can receive data words of either 8 or 9 bits. When the M bit is set, the word length

is 9 bits and the MSB is stored in the R8 bit in the SCICR1 register.

Character reception

During a SCI reception, data shifts in least significant bit first through the RDI pin. In

this mode, the SCIDR register consists or a buffer (RDR) between the internal bus and

the received shift register (see Figure 63).

Procedure:

–

Select the M bit to define the word length.

–

Select the desired baud rate using the SCIBRR and the SCIERPR registers.

–

Set the RE bit, this enables the receiver which begins searching for a start bit.

When a character is received:

–

The RDRF bit is set. It indicates that the content of the shift register is transferred

to the RDR.

–

An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR

–

The error flags can be set if a frame error, noise or an overrun error has been

detected during reception.

Clearing the RDRF bit is performed by the following software sequence done by:

An access to the SCISR register

A read to the SCIDR register.

The RDRF bit must be cleared before the end of the reception of the next character to

avoid an overrun error.

Break character

When a break character is received, the SCI handles it as a framing error.

Idle character

When an idle frame is detected, there is the same procedure as a data received

character plus an interrupt if the ILIE bit is set and the I bit is cleared in the CCR

ST72344S2 Datasheet(PDF) 135 Page - STMicroelectronics