ST72325AR7-Auto datasheet(148/243 Pages) STMICROELECTRONICS

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Serial communications interface (SCI)

ST72325xxx-Auto

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Doc ID 13770 Rev 3

A receiver wakes up by Idle Line detection when the Receive line has recognized an Idle

Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set.

Receiver wakes up by Address Mark detection when it received a ‘1’ as the most significant

bit of a word, thus indicating that the message is an address. The reception of this particular

word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the

receiver to receive this word normally and to use it as an address word.

Caution:

In Mute mode, do not write to the SCICR2 register. If the SCI is in Mute mode during the

read operation (RWU = 1) and a address mark wake-up event occurs (RWU is reset) before

the write operation, the RWU bit is set again by this write operation. Consequently the

address byte is lost and the SCI is not woken up from Mute mode.

Parity control

Parity control (generation of parity bit in transmission and parity checking in reception) can

be enabled by setting the PCE bit in the SCICR1 register. Depending on the frame length

defined by the M bit, the possible SCI frame formats are as listed in Table 71.

Legend: SB = Start Bit, STB = Stop Bit, PB = Parity Bit

Note:

In case of wake-up by an address mark, the MSB bit of the data is taken into account and

not the parity bit

Even parity: the parity bit is calculated to obtain an even number of ‘1’s inside the frame

made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.

Example: data = 00110101; 4 bits set => parity bit is 0 if even parity is selected (PS bit = 0).

Odd parity: the parity bit is calculated to obtain an odd number of ‘1’s inside the frame

made of the 7 or 8 LSB bits (depending on whether M is equal to 0 or 1) and the parity bit.

Example: data = 00110101; 4 bits set => parity bit is 1 if odd parity is selected (PS bit = 1).

Transmission mode: If the PCE bit is set then the MSB bit of the data written in the data

Reception mode: If the PCE bit is set then the interface checks if the received data byte

has an even number of ‘1’s if even parity is selected (PS = 0) or an odd number of ‘1’s if odd

parity is selected (PS = 1). If the parity check fails, the PE flag is set in the SCISR register

and an interrupt is generated if PIE is set in the SCICR1 register.

SCI clock tolerance

During reception, each bit is sampled 16 times. The majority of the 8th, 9th and 10th

samples is considered as the bit value. For a valid bit detection, all the three samples should

have the same value otherwise the noise flag (NF) is set. For example: If the 8th, 9th and

10th samples are 0, 1 and 1 respectively, then the bit value is ‘1’, but the Noise Flag bit is set

because the three samples values are not the same.

Table 71.

Frame formats

M bit

PCE bit

SCI frame

| SB | 8 bit data | STB |

| SB | 7-bit data | PB | STB |

| SB | 9-bit data | STB |

| SB | 8-bit data PB | STB |

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