ST72325AR7-Auto datasheet(149/243 Pages) STMICROELECTRONICS

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ST72325xxx-Auto

Serial communications interface (SCI)

Doc ID 13770 Rev 3

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Consequently, the bit length must be long enough so that the 8th, 9th and 10th samples

have the desired bit value. This means the clock frequency should not vary more than 6/16

(37.5%) within one bit. The sampling clock is resynchronized at each start bit, so that when

receiving 10 bits (one start bit, 1 data byte, 1 stop bit), the clock deviation must not exceed

3.75%.

Note:

The internal sampling clock of the microcontroller samples the pin value on every falling

edge. Therefore, the internal sampling clock and the time the application expects the

sampling to take place may be out of sync. For example: If the baud rate is 15.625 Kbaud

(bit length is 64µs), then the 8th, 9th and 10th samples are at 28µs, 32µs and 36µs

respectively (the first sample starting ideally at 0µs). But if the falling edge of the internal

clock occurs just before the pin value changes, the samples would then be out of sync by

~4us. This means the entire bit length must be at least 40µs (36µs for the 10th sample + 4µs

for synchronization with the internal sampling clock).

Clock deviation causes

The causes which contribute to the total deviation are:

–DTRA: Deviation due to transmitter error (Local oscillator error of the transmitter or

the transmitter is transmitting at a different baud rate).

–DQUANT: Error due to the baud rate quantization of the receiver.

–DREC: Deviation of the local oscillator of the receiver: This deviation can occur

during the reception of one complete SCI message assuming that the deviation

has been compensated at the beginning of the message.

–DTCL: Deviation due to the transmission line (generally due to the transceivers)

All the deviations of the system should be added and compared to the SCI clock tolerance:

DTRA + DQUANT + DREC + DTCL < 3.75%

Noise error causes

See also description of noise error in Receiver on page 144.

Start bit

The noise flag (NF) is set during start bit reception if one of the following conditions occurs:

A valid falling edge is not detected. A falling edge is considered to be valid if the 3

consecutive samples before the falling edge occurs are detected as ‘1’ and, after the

falling edge occurs, during the sampling of the 16 samples, if one of the samples

numbered 3, 5 or 7 is detected as a ‘1’.

During sampling of the 16 samples, if one of the samples numbered 8, 9 or 10 is

detected as a ‘1’.

Therefore, a valid Start Bit must satisfy both the above conditions to prevent the Noise Flag

getting set.

Data bits

The noise flag (NF) is set during normal data bit reception if the following condition occurs:

●

During the sampling of 16 samples, if all three samples numbered 8, 9 and10 are not

the same. The majority of the 8th, 9th and 10th samples is considered as the bit value.

Therefore, a valid Data Bit must have samples 8, 9 and 10 at the same value to prevent the

Noise Flag from getting set.

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