STM32F328C8 datasheet(24/109 Pages) STMICROELECTRONICS

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Functional overview

STM32F328C8

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DocID026351 Rev 3

In addition, it provides hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability,

Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and

ALERT protocol management. It also has a clock domain independent from the CPU clock,

allowing the I2C1 to wake up the MCU from Stop mode on address match.

The I2C interface can be served by the DMA controller.

Refer to Table 6 for the features available in I2C1.

3.16.2

Universal synchronous/asynchronous receiver transmitters (USARTs)

The STM32F328C8 devices have three embedded universal synchronous receiver

transmitters (USART1, USART2 and USART3).

The USART interfaces are able to communicate at speeds of up to 9 Mbits/s.

USART1 provides hardware management of the CTS and RTS signals. It supports IrDA SIR

ENDEC, the multiprocessor communication mode, the single-wire half-duplex

communication mode and has LIN Master/Slave capability.

All USART interfaces can be served by the DMA controller.

Refer to Table 7 for the features available in the USART interfaces.

Table 6. STM32F328C8 I2C implementation

I2C features(1)

1. X = supported.

I2C1

7-bit addressing mode

10-bit addressing mode

Standard mode (up to 100 kbit/s)

Fast mode (up to 400 kbit/s)

Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s)

Independent clock

SMBus

Wakeup from STOP

Table 7. USART features

USART modes/features(1)

USART1

USART2

USART3

Hardware flow control for modem

Continuous communication using DMA

Multiprocessor communication

Synchronous mode

Smartcard mode

Single-wire half-duplex communication

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