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STM32F303C6 Datasheet(PDF) 84 Page - STMicroelectronics |
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STM32F303C6 Datasheet(HTML) 84 Page - STMicroelectronics |
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84 / 115 page ![]() Electrical characteristics STM32F303x6/x8 84/115 DocID025083 Rev 5 SPI characteristics Unless otherwise specified, the parameters given in Table 55 for SPI are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 20: General operating conditions. Refer to Section 6.3.14: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI). Table 59. I2C analog filter characteristics(1) 1. Guaranteed by design, not tested in production. Symbol Parameter Min. Max. Unit tAF Maximum pulse width of spikes that are suppressed by the analog filter. 50(2) 2. Spikes with width below tAF(min.) are filtered. 260(3) 3. Spikes with width above tAF(max.) are not filtered. ns Table 60. SPI characteristics(1) Symbol Parameter Conditions Min Typ Max Unit fSCK 1/tc(SCK) SPI clock frequency Master mode 2.7<VDD<3.6 -- 24 MHz Master mode 2<VDD<3.6 18 Slave mode 2<VDD<3.6 24 Slave mode transmitter/full duplex 2<VDD<3.6 18(2) DuCy(SCK) Duty cycle of SPI clock frequency Slave mode 30 50 70 % tsu(NSS) NSS setup time Slave mode, SPI presc = 2 4*Tpclk - - ns th(NSS) NSS hold time Slave mode, SPI presc = 2 2*Tpclk - - tw(SCKH) tw(SCKL) SCK high and low time Master mode Tpclk-2 Tpclk Tpclk+2 tsu(MI) Data input setup time Master mode 0 - - tsu(SI) Slave mode 3 - - th(MI) Data input hold time Master mode 5 - - th(SI) Slave mode 1 - - ta(SO) Data output access time Slave mode 10 - 40 tdis(SO) Data output disable time Slave mode 10 - 17 tv(SO) Data output valid time Slave mode 2.7<VDD<3.6V - 12 20 Slave mode 2<VDD<3.6V - 12 27.5 tv(MO) Master mode - 1.5 5 th(SO) Data output hold time Slave mode 7.5 - - th(MO) Master mode 0 - - 1. Data based on characterization results, not tested in production. 2. Maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50%. |
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