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STM32L496QGI3STR Datasheet(PDF) 20 Page - STMicroelectronics |
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STM32L496QGI3STR Datasheet(HTML) 20 Page - STMicroelectronics |
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20 / 263 page  Functional overview STM32L496xx 20/263 DocID029173 Rev 2 The whole non-volatile memory embeds the error correction code (ECC) feature supporting: • single error detection and correction • double error detection. • The address of the ECC fail can be read in the ECC register 3.5 Embedded SRAM STM32L496xx devices feature 320 Kbyte of embedded SRAM. This SRAM is split into two blocks: • 256 Kbyte mapped at address 0x2000 0000 (SRAM1) • 64 Kbyte located at address 0x1000 0000 with hardware parity check (SRAM2). This memory is also mapped at address 0x2004 0000, offering a contiguous address space with the SRAM1. This block is accessed through the ICode/DCode buses for maximum performance. These 64 Kbyte SRAM can also be retained in Standby mode. The SRAM2 can be write-protected with 1 Kbyte granularity. The memory can be accessed in read/write at CPU clock speed with 0 wait states. |
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