STM32L496QGI3STR datasheet(40/263 Pages) STMICROELECTRONICS

40 / 263 page

Functional overview

STM32L496xx

40/263

DocID029173 Rev 2

3.15

Chrom-ART Accelerator™ (DMA2D)

The Chrom-Art Accelerator™ (DMA2D) is a graphic accelerator which offers advanced bit

blitting, row data copy and pixel format conversion. It supports the following functions:

•

Rectangle filling with a fixed color

•

Rectangle copy

•

Rectangle copy with pixel format conversion

•

Rectangle composition with blending and pixel format conversion.

Various image format coding are supported, from indirect 4bpp color mode up to 32bpp

direct color. It embeds dedicated memory to store color lookup tables.

An interrupt can be generated when an operation is complete or at a programmed

watermark.

All the operations are fully automatized and are running independently from the CPU or the

DMAs.

3.16

Interrupts and events

3.16.1

Nested vectored interrupt controller (NVIC)

The devices embed a nested vectored interrupt controller able to manage 16 priority levels,

and handle up to 90 maskable interrupt channels plus the 16 interrupt lines of the Cortex®-

M4.

The NVIC benefits are the following:

•

Closely coupled NVIC gives low latency interrupt processing

•

Interrupt entry vector table address passed directly to the core

•

Allows early processing of interrupts

•

Processing of late arriving higher priority interrupts

•

Support for tail chaining

•

Processor state automatically saved

•

Interrupt entry restored on interrupt exit with no instruction overhead

The NVIC hardware block provides flexible interrupt management features with minimal

interrupt latency.

3.16.2

Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of 41 edge detector lines used to generate

interrupt/event requests and wake-up the system from Stop mode. Each external line can be

independently configured to select the trigger event (rising edge, falling edge, both) and can

be masked independently A pending register maintains the status of the interrupt requests.

The internal lines are connected to peripherals with wakeup from Stop mode capability. The

EXTI can detect an external line with a pulse width shorter than the internal clock period. Up

to 136 GPIOs can be connected to the 16 external interrupt lines.

STM32L496QGI3STR Datasheet(PDF) 40 Page - STMicroelectronics

STM32L496QGI3STR Datasheet(HTML) 40 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL