84329AM-01

www.idt.com

REV. D

APRIL 9, 2014

4

84329-01

Inputs

Conditions

nP_LOAD

M

N

S_LOAD

S_CLOCK

S_DATA

X

X

X

X

X

X

Reset. M and N bits are all set HIGH.

L

Data

Data

X

X

X

Data on M and N inputs passed directly to M divider and

N output divider. TEST mode 000.

↑

Data

Data

L

X

X

Data is latched into input registers and remains loaded

until next LOW transition or until a serial event occurs.

HX

X

L

↑

Data

Serial input mode. Shift register is loaded with data on

S_DATA on each rising edge of S_CLOCK.

HX

X

↑

LData

Contents of the shift register are passed to the M divider

and N output divider.

HX

X

↓

L

Data

M divide and N output divide values are latched.

H

X

X

L

X

X

Parallel or serial input do not affect shift registers.

NOTE: L = LOW

H = HIGH

X = Don't care

↑ = Rising edge transition

↓ = Falling edge transition

VCO Frequency

(MHz)

M Divider

256

128

64

32

16

8

4

2

1

M8

M7

M6

M5

M4

M3

M2

M1

M0

200

200

0

1

1

0

0

1

0

0

0

201

201

0

1

1

0

0

1

0

0

1

202

202

0

1

1

0

0

1

0

1

0

203

203

0

1

1

0

0

1

0

1

1

•

•

•

•

••

••

•

•

•

•

•

•

•

••

••

•

•

•

509

509

1

1

1

1

1

1

1

0

1

510

510

1

1

1

1

1

1

1

1

0

511

511

1

1

1

111

111

NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.

Inputs

N Divider Value

Output Frequency (MHz)

N1

N0

Minimum

Maximum

0

0

1

200

700

0

1

2

100

350

10

4

50

175

1

1

8

25

87.5