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AS8C803600 Datasheet(PDF) 7 Page - Alliance Semiconductor Corporation

Part # AS8C803600
Description  Power down controlled by ZZ input
PDF  18 Pages
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Manufacturer  ALSC [Alliance Semiconductor Corporation]
Direct Link  https://www.alliancememory.com
Logo ALSC - Alliance Semiconductor Corporation

AS8C803600 Datasheet(HTML) 7 Page - Alliance Semiconductor Corporation

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AS8C803600, AS8C801800, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
3.3V I/O, Pipelined Outputs, Single Cycle Deselect
Commercial Temperature Range
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|ILI|
Input Leakage Current
VDD = Max., VIN = 0V to VDD
___
5µ A
|ILZZ|
ZZ and
LBO Input Leakage Current(1)
VDD = Max., VIN = 0V to VDD
___
30
µ A
|ILO|
Output Leakage Current
VOUT = 0V to VDDQ, Device Deselected
___
5µ A
VOL
Output Low Voltage
IOL = +8mA, VDD = Min.
___
0.4
V
VOH
Output High Voltage
IOH = -8mA, VDD = Min.
2.4
___
V
5310 tbl 08
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(VDD = 3.3V ± 5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test Load
AC Test Conditions
(VDDQ = 3.3V)
NOTE:
1. The
LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while
ADSC = LOW; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
VDDQ/2
50
Ω
I/O
Z0 =50
Ω
5310 drw 06 ,
1
2
3
4
20 30 50
100
200
∆tCD
(Typical, ns)
Capacitance (pF)
80
5
6
5310 drw 07
,
Symbol
Parameter
Test Conditions
166MHz
150MHz
133MHz
Unit
Com'l only
Com'l
Ind
Com'l
Ind
IDD
Operating Power Supply
Current
Device Selected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VIH or < VIL, f = fMAX(2)
340
305
325
260
280
mA
ISB1
CMOS Standby Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VHD or < VLD, f = 0(2,3)
50
50
70
50
70
mA
ISB2
Clock Running Power
Supply Current
Device Deselected, Outputs Open, VDD = Max.,
VDDQ = Max., VIN > VHD or < VLD, f = fMAX(2,3)
160
155
175
150
170
mA
IZZ
Full Sleep Mode Supply
Current
ZZ > VHD, VDD = Max.
50
50
70
50
70
mA
5310 tbl 09
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
0 to 3V
2ns
1.5V
1.5V
See Figure 1
5310 tbl 10



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