Theory of operation

STHVDAC-253M

10/27

DocID025735 Rev 1

3.4

RFFE serial interface

The HVDAC is fully controlled through RFFE serial interface (DATA, VIO, CLK).

This interface is further described in the next sections of this document and is made

compliant to the MIPI alliance Specification for RF Front End control Interface version 1.10

(26 July 2011)

Sequence Start Condition (SSC): One rising edge followed by falling edge on DATA while

CLK remains at logic level low. This is used by the Master to identify the start of a Command

frame.

Parity (P): Each frame shall end with a single parity bit. The parity bit shall be driven such

that the total number of bits in the frame that are driven to logic level one, including the

parity bit, is odd.

Bus Park Cycle (BP): The slave releasing DATA will drive the DATA to logic level zero

during the first half of the CLK clock cycle. This is used by the Master as the indication of the

end of Frame.

3.5

RFFE register and write command sequence

Register #0 is a specific register that can be programmed without sending the register

address. Output C is associated to Register #0 so that when there is only one tunable

capacitor to control a simple register#0 write command is sufficient. Please refer to

Figure 12

for Register #0 Write sequence. The Sequence Starts with an Start Sequence

command (SSC) followed by the Register #0 Write Command frame containing the slave

address, a logic one and a seven bit word to be written to Register #0.

3.6

RFFE serial interface extended mode

All the registers in the device can be addressed in extended mode, by sending appropriate

command sequences as per MIPI RFFE specification (see Figure 11).

3.7

RFFE serial interface broadcast capability

Registers 27 to 31 can be addressed in broadcast mode, by sending appropriate command

sequences as per MIPI RFFE specification.