M48T254V

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Figure 8. Memory READ Cycle

Note: WE is high for a READ cycle.

Figure 9. Memory WRITE Cycle, WRITE Enable Controlled

2. If the CE low transition occurs simultaneously with or later than the WE low transition in WE Controlled WRITE, the output buffers

remain in a high impedance state during this period.

3. If the CE high transition occurs simultaneously with the WE high transition, the output buffers remain in a high impedance state

during this period.

DQ0 - DQ7

ADDRESSES

OE

CE

DATA OUTPUT

VALID

tOD

tODO

tOE

tRC

tCO

tACC

tCOE

tCOE

tOH

AI04230

AI05655

DQ0–DQ7

ADDRESSES

WE

CE

DATA IN

STABLE

tAH1

tOEW

tDH1

tDS

tWC

tODW

tWP

tAW

HIGH IMPEDANCE