SA58643_1

© NXP B.V. 2006. All rights reserved.

Product data sheet

Rev. 01 — 20 November 2006

4 of 16

NXP Semiconductors

SA58643

Single-Pole Double-Throw (SPDT) switch

10. Static characteristics

[1]

The ENCH1 input must be connected to a valid logic level for proper operation of the SA58643.

11. Dynamic characteristics

[1]

The placement of the AC bypass capacitor is critical to achieve these specifications. See Section 13 “Application information” for more

details.

Table 5.

Static characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

supply current

40

170

300

µA

threshold voltage

TTL/CMOS logic

[1] 1.1

1.25

1.4

V

HIGH-level input voltage

logic 1 level; enable channel 1

2.0

-

V

LOW-level input voltage

logic 0 level; enable channel 2

−3.0

-

+0.8

V

LOW-level input current on pin ENCH1

ENCH1 = 0.4 V

−10

+1

µA

HIGH-level input current on pin ENCH1

ENCH1 = 2.4 V

−10

+1

µA

Table 6.

Dynamic characteristics

All measurements include the effects of the SA58643 evaluation board. Measurement system impedance is 50

Ω.

Symbol Parameter

Conditions

Min

Typ

Max

Unit

insertion power gain

DC to 100 MHz

-

1

-

dB

500 MHz

-

1.4

-

dB

900 MHz

-

2

2.8

dB

isolation

10 MHz

[1] 70

80

-

dB

100 MHz

-

60

-

dB

500 MHz

-

50

-

dB

900 MHz

24

30

-

dB

output return loss

DC to 400 MHz

-

20

-

dB

900 MHz

-

12

-

dB

input return loss

DC to 400 MHz

-

17

-

dB

900 MHz

-

13

-

dB

turn-off delay time

50 % TTL to (90 % to 10 %) RF

-

20

-

ns

turn-off fall time

90 % to 10 % RF

-

5

-

ns

turn-on rise time

10 % to 90 % RF

-

5

-

ns

peak-to-peak transient voltage

switching transients

-

165

-

mV

output power at 1 dB gain compression

DC to 1 GHz

-

+18

-

dBm

IP3

third-order intercept point

100 MHz

-

+33

-

dBm

IP2

second-order intercept point

100 MHz

-

+52

-

dBm

NF

noise figure

100 MHz

-

1.0

-

dB

900 MHz

-

2.0

-

dB