TLFD600

ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER

SLAS280B – MAY 2000 – REVISED NOVEMBER 2000

8

POST OFFICE BOX 655303

clock generation (continued)

Table 2. Clock Description

FREQUENCY (MHz)

CLOCK

CLKOUT_EN = 1

SYMMETRY

CLK1SEL = 0

CLK1SEL = 1

SCLK

35.328

35.328

50/50

CLK1OUT

20.187

15.701

43/57 for 20.187

44/56 for 15.701

CLK2OUT

4.096

4.096

49/51

serial interface

The serial interface on the TLFD600PAP will connect gluelessly to the C5000 or C6000 families of DSPs from

Texas Instruments. The serial interface operates at 35.328 MHz. The serial port is made up of five signals:

SCLK, FSX, FSR, SDX, and SDR. A typical connection diagram is shown in Figure 2.

CLKR

CLKX

FSX

FSR

DX

DR

SCLK

FSR

FSX

SDR

SDX

DSP

TLFD600PAP

Figure 2. Typical Serial Port Connection

The serial port utilizes a primary/secondary scheme to transfer conversion data and control register data

(command). A primary transfer is used to transfer conversion data. A secondary transfer is used to transfer

control data when requested by the host processor. The host processor requests a secondary transfer by using

the LSB of the SDR data of the primary transfer. A value of 1 indicates a secondary transfer request. Once the

secondary request is made and the primary transfer has completed, a secondary FSR pulse is transmitted to

the host processor to indicate the beginning of the secondary transfer. The secondary FSR signal arrives 48

SCLKs after the host processor request. Each bit is read/written at the rising edge of SCLK clock. Data bit

mappings and example data transfers are shown in Table 3.

Table 3. SDR LSB Control Function

CONTROL BIT D0

CONTROL BIT FUNCTION

0

No secondary transfer requested

1

Secondary transfer requested