DS1WM

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OPERATION — COMMANDS

The Command Register determines the DS1WM’s mode of operation and also handles special

transmissions over the bus. From this register the DS1WM can be selected to run in Overdrive mode,

Search ROM Accelerator mode, or standard mode. This register also controls bus resets, 1-Wire Master

resets, and direct reading and writing of the bus.

Command Register (Read/Write)

Addr. 00h

OD

X

RST

X

DQI

DQO

SRA

1WR

MSB

LSB

OD: Overdrive Bit. This bit selects the communication rate on the 1-Wire bus. Setting this bit to 1 will

allow high-speed communication if all slave devices on the bus support overdrive mode. This bit must be

set to 0 for standard 1-wire communication.

RST: Software Reset. Setting this bit will immediately stop any communication and reset all internal

state machines controlling communication. This command does not reset data in the registers. All register

data will be maintained, however the Interrupt Register may change to reflect the new state of the 1-Wire

Master. This bit must be 0 for normal operation.

DQO: DQ Output. This bit can be used to bypass 1-Wire Master operations and drive the bus directly if

needed. Setting this bit high will drive the bus low until it is cleared or the 1-Wire Master resets. While

the 1-Wire bus is held low no other 1-Wire Master operations will function. By controlling the length of

time this bit is set and the point when the line is sampled, see DQI below, any 1-Wire communication can

be generated by the host controller. To prevent accidental writes to the bus, the DQOE bit in the Interrupt

Enable Register must be set to a 1 before the DQO bit will function. This bit is cleared to a 0 on power-up

or Master Reset.

DQI: DQ Input. This bit is read only and reflects the present state of the 1-Wire bus. It should be used

together with the DQO bit when controlling the bus directly. The state of this bit does not affect any other

functions of the 1-Wire Master. Operation of this bit is unaffected by the state of DQOE.

1WR: 1-Wire Reset. If this bit is set a reset will be generated on the 1-Wire bus. Setting this bit

automatically clears the SRA bit. The 1WR bit will be automatically cleared as soon as the 1-Wire reset

completes. The 1-Wire Master will set the Presence Detect interrupt flag (PD) when the reset is complete

and sufficient time for a presence detect to occur has passed. The result of the presence detect will be

placed in the Interrupt Register bit PDR. If a presence detect pulse was received PDR will be cleared,

otherwise it will be set.

SRA: Search ROM Accelerator. When this bit is set, the 1-Wire Master will switch to Search ROM

Accelerator mode. This mode presupposes that a Reset followed by the Search ROM command (0xF0h)

has already been issued on the 1-Wire bus. For details on how the Search ROM is actually done in the 1-

Wire system, please see [1]. Simply put, the algorithm specifies that the bus master reads two bits (a bit

and its complement), then writes a bit to specify which devices should remain on the bus for further

processing.

After the 1-Wire Master is placed in Search ROM Accelerator mode, the CPU must send 16 bytes to

complete a single Search ROM pass on the 1-Wire bus. These bytes are constructed as follows: