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DS1WM Datasheet(PDF) 15 Page - Dallas Semiconductor

Part # DS1WM
Description  Synthesizable 1-Wire Bus Master
PDF  15 Pages
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Manufacturer  DALLAS [Dallas Semiconductor]
Direct Link  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS1WM Datasheet(HTML) 15 Page - Dallas Semiconductor

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DS1WM
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TIMING SPECIFICATIONS
Symbol
Parameter
Conditions
Min
Max
Units
t
ADS
Address Strobe Width
Note 1,3
60
ns
t
AH
Address Hold Time
Note 1,3
0
ns
t
AR
Address Latch to Read
Note 1,3
60
ns
t
AS
Address Setup Time
Note 1,3
60
ns
t
AW
Address Latch to Write
Note 1,3
60
ns
t
DH
Data Hold Time
Note 1
30
ns
t
DS
Data Setup Time
Note 1
30
ns
t
ES
Enable Setup Time
Note 1
60
ns
t
HZ
RD to Floating Data Delay
Note 1
0
100
ns
t
LOW0
Write 0 Low Time, OD=0
Write 0 Low Time, OD=1
63
t
8
t
63
8
78.75
10
µs
t
LOW1
Write 1 Low Time, OD=0
Write 1 Low Time, OD=1
6
t
1
t
6
1
7.5
1.25
µs
t
PDH
Presence Detect High Normal
Presence Detect High Overdrive
Note 4
26
2.6
60
6
µs
t
PDI
Presence Detect to INTR
Note 1
0
100
ns
t
PDL
Presence Detect Low Normal
Presence Detect Low Overdrive
Note 4
104
10.4
240
24
µs
t
PDS
Presence Detect Sample, OD=0
Presence Detect Sample, OD=1
30
t (Note 2)
3
t
30
3
37.5
3.75
µs
t
RD
RD Strobe Width
Note 1
125
ns
t
RDV
Read Data Valid Normal
Read Data Valid Overdrive
15
2
µs
t
REC
Recovery Time
1
µs
t
REN
Enable Hold Time from RD
Note 1
20
ns
t
RSTH
Reset Time High, OD=0
Reset Time High, OD=1
500
t
50
t
500
50
625
62.5
µs
t
RSTL
Reset Time Low, OD=0
Reset Time Low, OD=1
488
t
61
t
488
61
610
76.25
µs
t
RVD
Delay from RD to Data
Note 1
60
ns
t
SLOT
Time Slot, OD=0
Time Slot, OD=1
73
t
11
t
73
11
91.25
13.75
µs
t
Timebase Period
1
1.25
µs
t
WEN
Enable Hold Time from WR
Note 1
20
ns
t
WR
WR Strobe Width
Note 1
100
ns
t
WRST
WR High to Reset
Note 1
0
100
ns
NOTES:
1) These values will depend upon the process used to realize the circuit. Values shown are for example
purposes only.
2) The 1-Wire Master will wait for a falling edge on the DQ line to be detected after a reset, for up to 60
µs or 6 µs Overdrive.
3) If ADS is tied low, tAR and tAW are referred from tES ; thus RD or WR must occur at least
tES + tAR or tES + tAW after EN goes low.
4)
Timing determined by 1-wire slave
REFERENCES:
[1] Book of iButton Standards, Dallas Semiconductor, online at
http://www.ibutton.com/ibuttons/standard.pdf



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