S3A3 datasheet(5/139 Pages) RENESAS

5 / 139 page

R01DS0307EU0100 Rev.1.00

Page 5 of 139

Mar 7, 2017

S3A3

1. Overview

Overview

The S3A3 MCU integrates multiple series of software- and pin-compatible ARM®-based 32-bit MCUs that share a

common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development.

The MCU provides an optimal combination of low-power, high-performance ARM Cortex®-M4 core running up to

48 MHz with the following features:

 512-KB code flash memory

 96-KB SRAM

 Segment LCD Controller (SLCDC)

 Capacitive Touch Sensing Unit (CTSU)

 USB 2.0 Full-Speed Module (USBFS)

 14-bit A/D Converter (ADC14)

 12-bit D/A Converter (DAC12)

 Security features.

1.1

Function Outline

Table 1.1

ARM core

Feature

Functional description

ARM Cortex-M4

 Maximum operating frequency: up to 48 MHz

 ARM Cortex-M4

- Revision: r0p1-01rel0

- ARMv7E-M architecture profile

- Single precision floating-point unit compliant with the ANSI/IEEE Std 754-2008.

 ARM Memory Protection Unit (MPU)

- ARMv7 Protected Memory System Architecture

- 8 protect regions.

 SysTick timer

- Driven by LOCO clock.

Table 1.2

Memory

Feature

Functional description

Code flash memory

Maximum 512 KB code flash memory. See section 47, Flash Memory in User's Manual.

Data flash memory

8 KB data flash memory. See section 47, Flash Memory in User's Manual.

Option-setting memory

The option-setting memory determines the state of the MCU after a reset. See section 7,

Option-Setting Memory in User's Manual.

Memory Mirror Function (MMF)

The MMF can be configured to mirror the desired application image load address in code flash

memory to the application image link address in the 23-bit unused memory space (memory

mirror space addresses). Your application code is developed and linked to run from this MMF

destination address. The application code does not need to know the load location where it is

stored in code flash memory. See section 5, MMF (MMF) in User's Manual.

SRAM

On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC). An area in

SRAM0 provides error correction capability using ECC. See section 46, SRAM in User's

Manual.

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