S3A3 datasheet(8/139 Pages) RENESAS

8 / 139 page

R01DS0307EU0100 Rev.1.00

Page 8 of 139

Mar 7, 2017

S3A3

1. Overview

Table 1.7

Timers

Feature

Functional description

General PWM Timer (GPT)

The General PWM Timer (GPT) is a 32-bit timer with 4 channels and a 16-bit timer with 6

channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or

the up- and down-counter. In addition, PWM waveforms can be generated for controlling

brushless DC motors. The GPT can also be used as a general-purpose timer. See section 23,

General PWM Timer (GPT) in User's Manual.

Port Output Enable for GPT (POEG)

Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT)

output pins in the output disable state. See section 22, Port Output Enable for GPT (POEG) in

User's Manual.

Asynchronous General Purpose

Timer (AGT)

The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse

output, external pulse width or period measurement, and counting of external events.

This 16-bit timer consists of a reload register and a down-counter. The reload register and the

down-counter are allocated to the same address, and they can be accessed with the AGT

Realtime Clock (RTC)

The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count

mode, that are controlled by the register settings.

For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and

automatically adjusts dates for leap years.

For binary count mode, the RTC counts seconds and retains the information as a serial value.

Binary count mode can be used for calendars other than the Gregorian (Western) calendar.

See section 25, Realtime Clock (RTC) in User's Manual.

Table 1.8

Communication interfaces (1 of 2)

Feature

Functional description

Serial Communications Interface

(SCI)

The Serial Communication Interface (SCI) is configurable to five asynchronous and

synchronous serial interfaces:

 Asynchronous interfaces (UART and asynchronous communications interface adapter

(ACIA))

 8-bit clock synchronous interface

 Simple IIC (master-only)

 Simple SPI

 Smart card interface.

The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and

transmission protocol.

SCI0 and SCI1 have FIFO buffers to enable continuous and full-duplex communication, and

the data transfer speed can be configured independently using an on-chip baud rate generator.

See section 29, Serial Communications Interface (SCI) in User's Manual.

I2C Bus Interface (IIC)

The 3-channel IIC module conforms with and provides a subset of the NXP I2C bus (Inter-

Integrated Circuit bus) interface functions. See section 30, I2C Bus Interface (IIC) in User's

Manual.

Serial Peripheral Interface (SPI)

Two independent Serial Peripheral Interface (SPI) channels are capable of high-speed, full-

duplex synchronous serial communications with multiple processors and peripheral devices.

See section 32, Serial Peripheral Interface (SPI) in User's Manual.

Serial Sound Interface Enhanced

(SSIE)

The Serial Sound Interface Enhanced (SSIE) peripheral provides functionality to interface

digital audio devices for transmitting PCM audio data over a serial bus with the MCU. The

SSIE supports an audio clock frequency of up to 25 MHz, and can be operated as a slave or

master receiver/transmitter/transceiver to suit various applications. The SSIE includes 8-stage

FIFO buffers in the receiver and transmitter, and supports interrupts and DMA-driven data

reception and transmission. See section 35, Serial Sound Interface Enhanced (SSIE) in User's

Manual.

Quad Serial Peripheral Interface

(QSPI)

The QSPI is a memory controller for connecting a serial ROM (nonvolatile memory such as a

serial flash memory, serial EEPROM, or serial FeRAM) that has an SPI-compatible interface.

See section 33, Quad Serial Peripheral Interface (QSPI) in User's Manual.

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