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HT67F488 Datasheet(PDF) 52 Page - Holtek Semiconductor Inc |
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HT67F488 Datasheet(HTML) 52 Page - Holtek Semiconductor Inc |
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52 / 171 page  Rev. 1.60 5� �ove��e� ��� �016 HT67F488/HT67F489 TinyPowerTM A/D Flash MCU with LCD & EEPROM ThereisonlyonemethodofusingsoftwareinstructiontocleartheWatchdogTimer.Thatistouse thesingle“CLRWDT”instructiontocleartheWDT. Themaximumtimeoutperiodiswhenthe218divisionratioisselected.Asanexample,witha 32kHzLIRCoscillatorasitssourceclock,thiswillgiveamaximumwatchdogperiodofaround8 secondforthe218divisionratio,andaminimumtimeoutof8msforthe28divisionration. “ CLR WDT”Instruction 8-stage Divider WDT Prescaler WE4~WE0 bits WDTC Register Reset MCU LXT fSUB fSUB/28 8-to-1 MUX CLR WS2~WS0 (fSUB/28 ~ fSUB/218) WDT Time-out (28/fSUB ~ 218/fSUB) LIRC M U X FSUBC FSUB6~FSUB0 bits Watchdog Timer Reset and Initialisation Aresetfunctionisafundamentalpartofanymicrocontrollerensuringthatthedevicecanbeset tosomepredeterminedconditionirrespectiveofoutsideparameters.Themostimportantreset conditionisafterpowerisfirstappliedtothemicrocontroller.Inthiscase,internalcircuitrywill ensurethatthemicrocontroller,afterashortdelay,willbeinawelldefinedstateandreadyto executethefirstprograminstruction.Afterthispower-onreset,certainimportantinternalregisters willbesettodefinedstatesbeforetheprogramcommences.OneoftheseregistersistheProgram Counter,whichwillberesettozeroforcingthemicrocontrollertobeginprogramexecutionfromthe lowestProgramMemoryaddress. AnothertypeofresetiswhentheWatchdogTimeroverflowsandresets.Alltypesofresetoperations resultindifferentregisterconditionsbeingsetup.AnotherresetexistsintheformofaLowVoltage Reset,LVR,whereafullresetisimplementedinsituationswherethepowersupplyvoltagefalls belowacertainthreshold. Reset Functions Therearefourwaysinwhicharesetcanoccur,througheventsoccurringinternally. Power-on Reset Themostfundamentalandunavoidableresetistheonethatoccursafterpowerisfirstappliedto themicrocontroller.AswellasensuringthattheProgramMemorybeginsexecutionfromthefirst memoryaddress,apower-onresetalsoensuresthatcertainotherregistersarepresettoknown conditions.AlltheI/Oportandportcontrolregisterswillpowerupinahighconditionensuringthat allI/Oportswillbefirstsettoinputs. VDD Powe�-on Reset SST Ti�e-out tRSTD Note:tRSTDispower-ondelay,typicaltime=50ms Power-On Reset Timing Chart |
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