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R5F100GC Datasheet(PDF) 148 Page - Renesas Technology Corp

Part # R5F100GC
Description  True Low Power Platform
PDF  202 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F100GC Datasheet(HTML) 148 Page - Renesas Technology Corp

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RL78/G13
3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105
C)
Page 148 of 196
R01DS0131EJ0330 Rev.3.30
Mar 31, 2016
(3) During communication at same potential (CSI mode) (slave mode, SCKp... external clock input)
(TA =
40 to +105C, 2.4 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)
HS (high-speed main) Mode
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
20 MHz < fMCK
16/fMCK
ns
4.0 V
 EVDD0  5.5
V
fMCK
 20 MHz
12/fMCK
ns
16 MHz < fMCK
16/fMCK
ns
2.7 V
 EVDD0  5.5
V
fMCK
 16 MHz
12/fMCK
ns
16/fMCK
ns
SCKp cycle time
Note 5
tKCY2
2.4 V
 EVDD0  5.5 V
12/fMCK and 1000
ns
4.0 V
 EVDD0  5.5 V
tKCY2/2
 14
ns
2.7 V
 EVDD0  5.5 V
tKCY2/2
 16
ns
SCKp high-/low-level
width
tKH2,
tKL2
2.4 V
 EVDD0  5.5 V
tKCY2/2
 36
ns
2.7 V
 EVDD0  5.5 V
1/fMCK+40
ns
SIp setup time
(to SCKp
) Note 1
tSIK2
2.4 V
 EVDD0  5.5 V
1/fMCK+60
ns
SIp hold time
(from SCKp
) Note 2
tKSI2
2.4 V
 EVDD0  5.5 V
1/fMCK+62
ns
2.7 V
 EVDD0  5.5
V
2/fMCK+66
ns
Delay time from
SCKp
 to SOp output
Note 3
tKSO2
C = 30 pF
Note 4
2.4 V
 EVDD0  5.5
V
2/fMCK+113
ns
Notes 1. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp setup time becomes “to
SCKp
” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
2. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The SIp hold time becomes “from
SCKp
” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
3. When DAPmn = 0 and CKPmn = 0, or DAPmn = 1 and CKPmn = 1. The delay time to SOp output
becomes “from SCKp
” when DAPmn = 0 and CKPmn = 1, or DAPmn = 1 and CKPmn = 0.
4. C is the load capacitance of the SOp output lines.
5. Transfer rate in the SNOOZE mode : MAX. 1 Mbps
Caution
Select the normal input buffer for the SIp pin and SCKp pin and the normal output mode for the
SOp pin by using port input mode register g (PIMg) and port output mode register g (POMg).
Remarks 1.
p: CSI number (p = 00, 01, 10, 11, 20, 21, 30, 31), m: Unit number (m = 0, 1),
n: Channel number (n = 0 to 3), g: PIM number (g = 0, 1, 4, 5, 8, 14)
2.
fMCK: Serial array unit operation clock frequency
(Operation clock to be set by the CKSmn bit of serial mode register mn (SMRmn). m: Unit number,
n: Channel number (mn = 00 to 03, 10 to 13))
CSI mode connection diagram (during communication at same potential)
RL78
microcontroller
SCKp
SOp
SCK
SI
User device
SIp
SO



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