R5F100GC datasheet(150/202 Pages) RENESAS

150 / 202 page

RL78/G13

3. ELECTRICAL SPECIFICATIONS (G: INDUSTRIAL APPLICATIONS TA = -40 to +105

C)

Page 150 of 196

R01DS0131EJ0330 Rev.3.30

Mar 31, 2016

(4) During communication at same potential (simplified I

2C mode)

(TA =

40 to +105C, 2.4 V  EVDD0 = EVDD1  VDD  5.5 V, VSS = EVSS0 = EVSS1 = 0 V)

HS (high-speed main)

Mode

Parameter

Symbol

Conditions

MIN.

MAX.

Unit

2.7 V

 EVDD0  5.5 V,

Cb = 50 pF, Rb = 2.7 k



400

Note1

kHz

SCLr clock frequency

fSCL

2.4 V

 EVDD0  5.5 V,

Cb = 100 pF, Rb = 3 k



100

Note1

kHz

2.7 V

 EVDD0  5.5 V,

Cb = 50 pF, Rb = 2.7 k



1200

Hold time when SCLr = “L”

tLOW

2.4 V

 EVDD0  5.5 V,

Cb = 100 pF, Rb = 3 k



4600

2.7 V

 EVDD0  5.5 V,

Cb = 50 pF, Rb = 2.7 k



1200

Hold time when SCLr = “H”

tHIGH

2.4 V

 EVDD0  5.5 V,

Cb = 100 pF, Rb = 3 k



4600

2.7 V

 EVDD0  5.5 V,

Cb = 50 pF, Rb = 2.7 k



1/fMCK + 220

Note2

Data setup time (reception)

tSU:DAT

2.4 V

 EVDD  5.5 V,

Cb = 100 pF, Rb = 3 k



1/fMCK + 580

Note2

2.7 V

 EVDD0  5.5 V,

Cb = 50 pF, Rb = 2.7 k



770

Data hold time (transmission)

tHD:DAT

2.4 V

 EVDD0  5.5 V,

Cb = 100 pF, Rb = 3 k



1420

Notes 1. The value must also be equal to or less than fMCK/4.

2. Set the fMCK value to keep the hold time of SCLr = "L" and SCLr = "H".

Caution

Select the normal input buffer and the N-ch open drain output (VDD tolerance (for the 20- to 52-pin

products)/EVDD tolerance (for the 64- to 100-pin products)) mode for the SDAr pin and the normal

output mode for the SCLr pin by using port input mode register g (PIMg) and port output mode

(Remarks are listed on the next page.)

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