HT82V70 datasheet(21/71 Pages) HOLTEK

21 / 71 page

Rev. 1.00

January 12, 2017

HT82V70

• Address P0_11h: Data Path Control Register 1

Bit

Mode

Description

Default

7-6

R/W

Video Port VD signal selection

00: V sync

01: V valid

10: H sync

11: H valid

5-4

R/W

Video Port HD signal selection

00: V sync

01: V valid

10: H sync

11: H valid

3-2

—

Reserved

—

R/W

Video Port clock out polarity selection

0: Positive edge

1: Negative edge

Shading/DSP Transfer Done

Note: only for Shading Ram ↔ DSP

—

• Address P0_12h: Data Path Control Register 2

Bit

Mode

Description

Default

7-3

—

Reserved

R/W

CIS Data Output Order on Video Port

0: Big endian

1: Little endian

Note: 1. If P0_10[6] is pixel-by-pixel and big endian is chosen, then the

data output format is {CIS1[7:0], CIS2[7:0]} and vice versa.

2. If P0_10[6] is line-by-line and big endian is chosen, the data

output format is {CIS1_0[7:0], CIS1_1[7:0]}, {CIS1_2[7:0],

CIS1_3[7:0]}, …{CIS2_0[7:0], CIS2_1[7:0]}, {CIS2_2[7:0],

CIS2_3[7:0]}

R/W

Line wait enable

0: Disable

1: Enable

Note: If Line wait enable and Output Data Format is "Line-by-Line"

as set in register P0_10[6], after the CIS1 data of a line has

been transferred, the CIS2 data will not be transferred until the

counter reaches the value set by registers P0_13h and P0_14h

R/W

CIS2 Lamp Control Selection

0: Depend on tg1,CIS1 Lamp, mode relative register

1: Depends on tg2,CIS2 Lamp, mode relative registers

Note: When CIS2 Lamp Control Selection is not set; CIS2 light signals

only depend on TG1 and CIS1 lamp control, mode relative registers

and TG2 and CIS2 registers are ignored.

• Address P0_13h: Line Wait Counter MSB Register

Bit

Mode

Description

Default

7-0

R/W

Line Wait Counter MSB

Note: Counter is based on the VPFE clock

00h

• Address P0_14h: Line Wait Counter LSB Register

Bit

Mode

Description

Default

7-0

R/W

Line Wait Counter LSB

Note: Counter is based on the VPFE clock

00h

HT82V70 Datasheet(PDF) 21 Page - Holtek Semiconductor Inc

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