HT82V70 datasheet(39/71 Pages) HOLTEK

39 / 71 page

Rev. 1.00

January 12, 2017

HT82V70

• Address P3_1Ah: TG CIS_2 CH_3/6 End of Valid Pixels LSB Register

Bit

Mode

Description

Default

7-0

R/W

End of Valid Pixels – Least Significant Byte.

Selects the pixel count where the data status bits stop indicating valid

pixels.

Notes: 1. End valid pixels mean distance from falling edge of SH to

end of valid pixel.

2. If the channel_3/6 start valid pixel and the end valid pixel

3. "End valid pixel – Start valid pixel + 1 " should be even.

40h/40h

• Address P3_1Bh: TG CIS_2 Line Valid Start and End MSB Register

Bit

Mode

Description

Default

7-4

R/W

AFE2 Line Valid Start Value – Most Significant 4 Bits

Selects the Line count where the valid line is started after BOS

3-0

R/W

AFE2 Line Valid End Value – Most Significant 4 Bits

Selects the Line count where the valid line is ends after BOS

• Address P3_1Ch: TG CIS_2 Line Valid Start LSB Register

Bit

Mode

Description

Default

7-0

R/W

AFE2 Line Valid Start Value – Least Significant Byte

Selects the Line count where the valid line is ends after BOS

00h

• Address P3_1Dh: TG CIS_2 Line Valid End LSB Register

Bit

Mode

Description

Default

7-0

R/W

AFE2 Line Valid End Value – Least Significant Byte

Selects the Line count where the valid line ends after BOS

Note: When line valid Start and End are equal to zero, the line is

always valid after BOS.

00h

• Address P3_1Eh: CIS Channel Switching Selection Register

Bit

Mode

Description

Default

—

Reserved

—

R/W

CIS2_CH_3/6 Setting Selection Register

0: CIS2_CH_3 Register Setting

1: CIS2_CH_6 Register Setting

Note: CIS2_CH_3/CIS2_CH_6 Setting on register P3_17~P3_1A is

set by this bit.

R/W

CIS2_CH_2/5 Setting Selection Register

0: CIS2_CH_2 Register Setting

1: CIS2_CH_5 Register Setting

Note: CIS2_CH_2/CIS2_CH_5 Setting on register P3_13~P3_16 is

set by this bit.

R/W

CIS2_CH_1/4 Setting Selection Register

0: CIS2_CH_1 Register Setting

1: CIS2_CH_4 Register Setting

Note: CIS2_CH_1/CIS2_CH_4 Setting on register P3_0F~P3_12 is

set by this bit.

—

Reserved

—

R/W

CIS1_CH_3/6 Setting Selection Register

0:CIS1_CH_3 Register Setting

1:CIS1_CH_6 Register Setting

Note: CIS1_CH_3/CIS1_CH_6 Setting on register P3_08~P3_0B is

set by this bit.

R/W

CIS1_CH_2/5 Setting Selection Register

0: CIS1_CH_2 Register Setting

1: CIS1_CH_5 Register Setting

Note: CIS1_CH_2/CIS1_CH_5 Setting on register P3_04~P3_07 is

set by this bit.

HT82V70 Datasheet(PDF) 39 Page - Holtek Semiconductor Inc

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