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RT4730WSC Datasheet(PDF) 16 Page - Richtek Technology Corporation |
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RT4730WSC Datasheet(HTML) 16 Page - Richtek Technology Corporation |
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16 / 17 page ![]() RT4730 16 DS4730-01 March 2017 www.richtek.com © Copyright 2017 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation. Layout Considerations For the best performance of the RT4730, the following PCB layout guidelines should be strictly followed. For good regulation, place the power component as close to the IC as possible. The traces should be wide and short especially for the high current output loop. The input and output bypass capacitor should be placed as close the IC as possible and connected to the ground plane of the PCB. The flying capacitor should be placed as close to the C1P/C1N pin as possible to avoid noise injection. The inductor should be placed as close to LX1 and LX2 pin for reducing EMI. Minimize the size of the LX1 and LX2 and keep the traces wide and short. Care should be taken to avoid running traces that carry any noise-sensitive signals near LX1 and LX2 Figure 2. PCB Layout Guide LX1 PGND C1N 2 SWIRE AVDDEN VON VOUT OVDD AVDD OVSS AGND CPGND AVIN PVIN GND LX L1 C8 VBAT C1 C6 GROUND GROUND SWIRE AVDD OVSS C4 OVDD C5 VON GROUND WL-CSP-16B 2.34x2.34 (BSC) AVDDEN C3 GROUND C7 C9 P 1 C The flying capacitor should be placed as close to C1P/C1N pin as possible to avoid noise injection. The inductor should be placed as close to LX1 and LX2 pin for reducing EMI. Minimize the size of the LX1 and LX2 and keep the traces wide and short. Care should be taken to avoid running traces that carry any noise-sensitive signals near LX1 and LX2. The output bypass capacitor should be placed as close the IC as possible and connected to the ground plane of the PCB. Connect AGND、 PGND、CPGND in top layer. The input bypass capacitor should be placed as close the IC as possible and connected to the ground plane of the PCB. |
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