UCC24612

SR

30

UCC24612

SLUSCM5 – AUGUST 2017

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10 Layout

10.1 Layout Guidelines

The printed circuit board (PCB) requires conscientious layout to minimize current loop areas and track lengths,

especially when using single-sided PCBs.

•

Place a ceramic MLCC bypass capacitor as close as possible to VCC and GND.

•

Avoid connecting VD and VS sense points at locations where stray inductance is added to the SR MOSFET

package inductance, as this will tend to turn off the SR prematurely.

•

Run a track from the VD pin directly to the MOSFET drain pad to avoid sensing voltage across the stray

inductance in the SR drain current path.

•

Run a track from the VS pin directly to the MOSFET source pad to avoid sensing voltage across the stray

inductance in the SR source current path. Because this trace shares both the gate driver path and the

MOSFET voltage sensing path, it is recommended to make this trace as short as possible.

•

Run parallel tracks from GATE and GND to the SR MOSFET. Include a series gate resistance to dampen

ringing.

10.2 Layout Example

Figure 25. PCB Layout for Driving an SR with SO-8 Package