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EVAL-AD7902SDZ Datasheet(PDF) 27 Page - Analog Devices |
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EVAL-AD7902SDZ Datasheet(HTML) 27 Page - Analog Devices |
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27 / 29 page ![]() AD7902 Data Sheet Rev. B | Page 26 of 28 LAYOUT Design the printed circuit board (PCB) of the AD7902 such that the analog and digital sections are separated and confined to certain areas of the board. The pinout of the AD7902, with its analog signals on the left side and its digital signals on the right side, eases this task. Avoid running digital lines under the device because these couple noise onto the die unless a ground plane under the AD7902 is used as a shield. Do not run fast switching signals, such as CNVx or clocks, near analog signal paths. Avoid crossover of digital and analog signals. To avoid signal fidelity issues, take care to ensure monotonicity of digital edges in the PCB layout. Use at least one ground plane. It can be shared between or split between the digital and analog sections. In the latter case, join the planes underneath the AD7902. The AD7902 voltage reference inputs, REF1 and REF2, have a dynamic input impedance. Decouple these reference inputs with minimal parasitic inductances by placing the reference decoupling ceramic capacitor in close proximity to (ideally, right up against) the REFx and GND pins and then connecting them with wide, low impedance traces. Finally, decouple the power supplies, VDDx and VIOx, with ceramic capacitors, typically 100 nF. Place them in close proximity to the AD7902 and connect them using short, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. See Figure 53 for an example of layout following these rules. EVALUATING PERFORMANCE OF THE AD7902 Other recommended layouts for the AD7902 are outlined in the EVAL-AD7902SDZ User Guide. The package for the evaluation board (EVAL-AD7902SDZ) includes a fully assembled and tested evaluation board, user guide, and software for controlling the board from a PC via the EVAL-SDP-CB1Z. Figure 53. Example Layout of the AD7902 (Top Layer) REF1 VDD1 IN1+ IN1– GND REF2 VDD2 IN2+ IN2– GND VIO1 SDI1 SCK1 SDO1 CNV1 VIO2 SDI2 SCK2 SDO2 CNV2 GND REF REF REF GND GND GND VDD VDD GND VIO VIO GND |
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